Long Live the (8 Bit) King

There are whispers that their time has come to fade away into the sunset. Time to drift away on the electronic wind with laser discs, Zune players, and VHS. But can the role of 8 bit MCUs in the electronic engineering ecosystem be dismissed so easily? Maybe not. In this week’s episode of Fish Fry, Nikos Zervas (CEO … Read More → "Long Live the (8 Bit) King"

Is AI the Killer FPGA Application?

Ross Freeman, co-founder of Xilinx, invented the FPGA in 1984. In the 34 years that have passed, FPGAs have been wildly successful and are certainly among the most important electronic devices ever conceived. But during that entire history, tracing the evolution of FPGAs from dozens of LUTs to millions, the FPGA has been the optimal solution for … exactly zero applications.

Don’t get me wrong. FPGAs do one thing … Read More → "Is AI the Killer FPGA Application?"

July 16, 2018
July 13, 2018
July 12, 2018
July 10, 2018
July 9, 2018
July 6, 2018
July 5, 2018
July 3, 2018
July 2, 2018
discussion
Posted on Jul 16 at 9:48am by Bryon Moyer
What do you think of Applied's tapping cobalt for interconnect?
Posted on Jul 16 at 5:41am by appleseed314
If the algorithm isn’t memory bound at all, then a highly pipelined superscalar high core count CPU/GPU implementation is likely to be as fast, or faster than an FPGA. While it's possible to be faster than an FPGA with high core count, it's probably not economical energy wise. ...
Posted on Jul 12 at 2:48pm by TotallyLost
We write algorithms based on the communications structure of the hardware it runs on. Most problems can be expressed with very different algorithms that are highly optimal for different highly parallel cpu, memory, and communications architectures. When single processor/memory systems are targeted, we tend to write monolithic algorithms and ...
Posted on Jul 11 at 1:18pm by ericverhulst
It all depends on the application. The key differentiator here might be the front-end. Design the application from the start as independent parallel processing "processes" (in essence, forget the global state machine) and the rest follows without headaches. Remember the transputer? It was based on the CSP process algebra. Even ...
Posted on Jul 11 at 11:51am by Jim Turley
What do you think? Are EDGE processors the wave of the future, or just another interesting science project for CPU nerds?
Posted on Jul 11 at 1:15am by TotallyLost
The primary bottleneck in CPU/GPU solutions is serialization from memory, even with large multi-level caches. If you can fit the algorithm in L1 cache, then it can go fast. Amdahl's law kicks in. The speedup that FPGA's provide, is that you can remove many of the serial memory accesses, ...
Posted on Jul 11 at 12:33am by Christoforos
FPGAs can provide much higher performance but there is still the problem of programmability as it is mentioned in the article. The only way to make is widely available to the cloud/ML users is through the use of libraries/cores that are completely transparent to the users and there ...
Posted on Jul 10 at 11:47am by Karl Stevens
The flexibility of FPGAs is overkill. The result being that too much time, power, and cost is in the fabric. Microprogramming was used for years in CPU controls because it is much easier than RTL design and there is a lot of flexibility to change algorithms. Another thing that is ...
Posted on Jul 9 at 9:35am by Bryon Moyer
What do you think of eSilicon's neuASIC approach?
Posted on Jul 6 at 8:01am by Karl Stevens
Not only x86, but the whole RISC approach is doddering. Especially for embedded systems and compute intensive systems where accelerators are popular. RISC is primarily justified on the ability of compilers to generate native code, BUT the reality is that there is a thing called Intermediate Language (CIL, MSIL, etc.) ...
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featured blogs
Jul 16, 2018
This week it is CDNLive Japan on Friday July 20th. I will be there so obviously this will be my latest trip to Japan...but we will start by looking at my first trip to Japan. The first trip I made to Japan was in 1983. This was very early. If you have been in semiconductors o...
Jul 12, 2018
A single failure of a machine due to heat can bring down an entire assembly line to halt. At the printed circuit board level, we designers need to provide the most robust solutions to keep the wheels...
Jun 29, 2018
Once you'€™ve made the correct decision to add Speedcore eFPGA IP to your ASIC or SoC design, the next question you'€™ll need to answer is how large to make the eFPGA. That'€™s a multi-dimensional question because Speedcore eFPGAs contain many types of blocks including:...
chalk talks
Maxim’s Himalaya uSLIC Solution: Industry’s Smallest Power Modules   New ultra-small power modules can deliver smaller solution size, higher reliability, and higher power density. In this episode of Chalk Talk, Amelia Dalton chats with John Woodward from Maxim Integrated about the industry’s smallest power modules. They might be exactly what you need for your next design. Click here for more information about … Read More → "Maxim’s Himalaya uSLIC Solution: Industry’s Smallest Power Modules"
Scaling Up Vision and AI DSP Performance  For high-performance, low-power processing of AI and machine vision algorithms, latency can be critical. In this episode of Chalk Talk, Amelia Dalton chats with Pulin Desai from Cadence Design Systems about the using the new Vision Q6 processor core for embedded vision and AI applications. Click here for more information about Vision DSPs for … Read More → "Scaling Up Vision and AI DSP Performance"
KSIM: Capacitors  Finding the right capacitor for your design can be a challenge. Many designers don’t take the time to research the best capacitor for their application, and this can result in increased cost, reduced performance, and reduced reliability. In this episode of Chalk Talk, Amelia Dalton chats with Wilmer Companioni of KEMET about KSIM – … Read More → "KSIM: Capacitors"
Designing 5G Wireless Technologies with MATLAB and Simulink  5G wireless infrastructure brings daunting design challenges. Fortunately, tools are available that can model and simulate some of the most complex aspects of 5G design. In this episode of Chalk Talk, Amelia Dalton chats with Ken Karnofsky of MathWorks about modeling and simulation for beamforming, RF power amplifier linearization, and much more. Click here … Read More → "Designing 5G Wireless Technologies with MATLAB and Simulink"
Synergy Platform Update IoT development demands a laundry list of specialized technologies and design decisions. It pays to have a development platform that can keep up with the rapidly changing landscape. In this episode of Chalk Talk, Amelia Dalton chats with Henrik Floodell from Renesas about how the latest version of the Synergy Platform can help keep … Read More → "Synergy Platform Update"
Maxim’s DARWIN Low Power Microcontrollers   MCUs continue to evolve based on increasing demands from designers. We expect our microcontrollers to do more than ever – better security, more performance, lower power consumption – and we want it all for less money, of course. In this episode of Chalk Talk, Amelia Dalton chats with Kris Ardis from Maxim Integrated … Read More → "Maxim’s DARWIN Low Power Microcontrollers"