From the Editor
Marketing people have been trying for years to figure out the best ways to reach professional engineers. We are, apparently, an elusive prey. Recently, there has been much wringing of hands with the realization that engineers don't act like "normal" people when it comes to virtual communication channels like facebook, twitter, virtual conferences, and online chat. Are the people who create technology techno-phobic? Do we slave away all day over hot oscilloscopes just to go home at night to a life of log cabins, wood fires, and vegetable gardens? This week, we look at the role virtual communications play in the life of a fictitious but not-that-unrealistic engineer.
We've extended the deadline for the final Journal Forum Posting competition. Post something creative and you could walk away with the final $500 amazon.com gift certificate!
Thanks as always for reading. We encourage you to share your thoughts in the new easier-to-use comments area right below the articles; don't be shy. Or you can get a lively discussion going on our new FORUMS.
Kevin Morris - Editor, FPGA Journal
Industry News
September 01, 2010
Tiny Low Frequency Clock Chip Supports Long Duration Timing from 1ms to 9.5hrs
C-to-FPGA Integration Accelerates Prototyping 10X
August 31, 2010
Technical Education on Digital Signal Processing, FPGAs and Embedded Processors
HDL Works Presents 'IO Checker 2.0'
August 30, 2010
SoCIP Road Shows to Stop at Shenzhen, Chengdu and Xi’an
S2C Announces Virtex-6 Based 4th Generation Rapid SoC Prototyping Solution
2A, 42V Boost Converter Now Offered in High Temperature "H" & "MP" Grades
August 26, 2010
August 25, 2010
Synopsys DesignWare SATA IP Enables First-Pass Silicon Success for Global Unichip Corporation
Microsoft Research uses Lyrtech SFF SDR development platform for experimental ‘white space’ device
7-Channel I2C-Controlled PMIC for High Power 1-Cell Li-Ion Systems
August 24, 2010
Mercury Computer Systems Launches Intel Core i7-Based OpenVPX Solutions for ISR Applications
Synopsys Announces Immediate Availability of DesignWare MIPI M-PHY IP in 40-nm Process Technology
Rail-to-Rail SiGe Op Amps Offer Unmatched Speed-Power Efficiency
August 23, 2010
Synopsys to Host First Synposium Virtual Event
August 19, 2010
Unison Ultra Tiny Linux OS Now Available for Actel SmartFusion Devices
August 18, 2010
InPA Systems Inc. Targets Active Debug™ for Rapid Prototyping
Feature Articles
Socially Inept
Do Engineers Fail at Virtual Connections?
It's 4:45AM. Charles hits "snooze" one last time on his alarm clock. He can wait another 8 minutes before trying to really wake up for his 5AM conference call with Europe. His status report is 80% finished on his laptop, which waits in "hibernate" by his bed. His smartphone is on his nightstand, next to his bluetooth headset. He tells himself he's pretty much ready for the meeting.
4:53AM - the alarm beeps again and Charles forces his eyelids apart, rolls out of bed and stumbles down the hallway to the kitchen. The espresso machine is already warmed up. He drops in a coffee pod, places a cup below the spout, and presses the "Lungo" button. He wants the extra kick to keep him awake through his call. The 60-second espresso pull feels like an eternity and he bats his eyes into focus as the dark brown liquid slowly lightens. Finally, the machine clicks to a stop and he trundles back down the hall toward his bed, cuddling the warm mug with both hands. Read More
Debug Doppelgänger
InPA Aims to Simplify FPGA-based Prototypes
There is an I After All
But Seriously, Folks, It was a Team Effort
Adept Alternative
Aldec Turns up the Simulation Heat
Xilinx Pwns Space
Is New Rad-Hard FPGA Family a Game-Changer?
Persistent Precision
Mentor Synthesis Makes Steady, Stealthy Progress
Lattice Turns up the Tools
Diamond Re-vamps Design Experience
Observations: 1. Charles needs
1. Charles needs some trust-worthy spam control.
2. I'm Charles in so many ways.
3. Ditto Remy, except maybe "Charles gets around to reading his FPGA Journal four days after it arrives electronically."
Fun post.
Nice story, but you forgot the F
Are Engineers Socially Inept or Just Busy?
FPGA-based Prototyping
Functional coverage & random gen - when do we converge?
You raised 2 important discussions here - one on ABV and the other on CDV. Let me provide my views on CDV here.
As you have noted, you ran 30-50K random vectors, still not sure..that's always the case unless you have an ...