Algorithms to Silicon  
Using Prototype Boards to Accelerate System-level Verification
Tom Feist , VP Sales and Marketing, AccelChip Inc.

In 1999 NASA lost the Climate Orbiter while in route to Mars. Failure to recognize and correct an error in a transfer of information between the Colorado spacecraft team and the California-based navigation team resulted in the loss of the $125 million spacecraft. The engineering failure was due to the fact that one team used English units while the other used metrics for a key spacecraft operation. It just goes to show that the slightest error or miscalculation can lead to catastrophic results.

Veteran designers should always keep a couple of old clichés in mind: “Everything that can go wrong will go wrong” and “Hindsight is always 20/20.” Experience has proven the critical bug always shows up in the one area that you didn’t have time to simulate. It seems obvious after the fact, but by then it’s too late. However, system-level verification can decrease the chance of errors when building digital signal processing (DSP) chips.

For the architectural specification, using a design-specific language can facilitate verification of the design. According to Will Straus, President of Forward Concepts, the majority of today’s critical DSP algorithms begin in MATLAB® (see “What is the Right Language for DSP System-Level Design”). This is because of the tool’s powerful yet easy-to-use algorithm development and visualization environment. Unfortunately, while MATLAB’s floating-point performance is exceptional, performance falls off rapidly after quantization (floating-point to fixed-point conversion).

In addition, companies face a major discontinuity between the algorithm development and the working silicon. Generally there is not one golden source, so while the algorithm is verified, the path to silicon requires manual creation of RTL, which lowers the level of abstraction. As the abstraction level goes down, so does the verification performance…significantly. To avoid a disaster, or at a minimum a design iteration, the system should be verified at all levels of abstraction.

To mitigate risk and increase verification performance, many companies are now applying a methodology called “hardware in the loop” ( HIL ). HIL has been defined as “a simulation technique where an electronic system simulates the behavior of a physical system.” It is used to increase verification of key algorithms in order to validate new products before they go into production.

While HIL was once relegated to multimillion dollar emulation systems, the increased size and performance of FPGAs has opened the door to new offerings of relatively inexpensive prototyping boards which can be used as HIL solutions tailored for specific vertical markets. For example, Nallatech and GiDEL both offer systems that provide key interfaces and resources for image processing, data processing, digital signal processing, and communications systems. Nallatech’s platform utilizes Xilinx Virtex-II Pro® and Spartan-II® based systems, while GiDEL offers the same performance with Altera Stratix™ and Apex™ platforms. They both provide a plug-and-play platform that is at the heart of today’s HIL systems.

But, is the time and effort on using HIL worth it? Consider a scenario where you lead a team assigned the design of a new autopilot for the next-generation Predator unmanned aircraft. If your terrain-following algorithm is just a bit off, every design iteration without HIL could have a price tag of about $5 million (the cost of the plane that you just crashed during debug). The incremental costs and flow challenges associated with HIL will seem negligible when you look at it this way.

However, for HIL to reach its full potential, design teams require a closed-loop, rapid prototyping environment that puts hardware in the hands of algorithm designers and automates the path to silicon. This facilitates rapid verification of the results on hardware while enabling easy algorithm level tweaks.

Take, for example, a design team who needs to implement an edge detection algorithm for a new product. Edge detection was first developed for satellite image enhancement and is now a mainstay of digital image processing. Edge detection is useful in a variety of image processing applications including image enhancement, coding, restoration and recognition. The first stage in many edge detectors is a process of enhancement that generates an image in which ridges correspond to statistical evidence for an edge. Such a process is often referred to as edge enhancement and is achieved using a class of linear convolution operators (often named after their inventors) including "Roberts," "Prewitt," and the early stages of "Canny." An edge is detected by changes in pixel intensity.

A design like this lends itself to a MATLAB environment; however, implementing and validating a new product that includes edge detection could take months. Once the manual process of creating the RTL from MATLAB is completed, it requires thousands of pictures through the design to make sure the “local variance” and “signal-to-noise ratios” are tuned to obtain the optimum performance. With HIL, this task can be accomplished in days versus weeks using RTL simulation. This increased verification performance and coverage, combined with rapid iterations at the algorithmic level, can combine to dramatically decrease development time.

The demand for a more efficient path from algorithm to silicon that can be verified with HIL has given rise to a new breed of DSP Design Automation (DDA) companies such as AccelChip Inc. AccelChip bridges the gap between DSP algorithm development and FPGA and ASIC implementation. Its vendor-independent flow enables designs to be rapidly targeted to FPGAs for verification with HIL and then retargeted to an ASIC or structured ASIC if required for production. The company has partnered with HIL providers such as Nalletech and GiDEL to provide a true top down synthesis environment that accelerates design and implementation of MATLAB-based DSP designs. The AccelChip® DSP Synthesis tool automatically synthesizes MATLAB as a “golden source,” provides a closed-loop verification environment for algorithm designers, and offers the ability to use HIL as part of a rapid design exploration solution.

HIL will continue to gain popularity as the expense of bringing new hardware products to market continues to increase. As more companies adopt this methodology, DDA, EDA and board manufacturers will need to continue to work closer to provide end users with a complete solution from algorithms to silicon.

For a more complete overview of how HIL can be used as part of a complete algorithms-to-silicon flow, contact AccelChip at 408-943-0700 . Or, go to http://www.accelchip.com/dac/index.html to sign up for a demonstration at this year’s Design Automation Conference.

Tom Feist , VP Sales and Marketing, AccelChip Inc.

May 11, 2004

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