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As DSP design teams transition to hardware implementation of DSP algorithms for higher performance, a new DSP design methodology is required to automate the flow from algorithms to silicon. by Dan Ganousis, AccelChip, Inc. Introduction We’re on the threshold of the next wave of rapid growth in high technology. During the 1970s, we witnessed the proliferation of semiconductors that enabled the digital generation. In the 1980s came the decade of dynamic memories (DRAMs) as semiconductor vendors perfected their manufacturing technologies to allow dramatic increases in memory capacity at previously unheard of prices. The 1990s will be remembered as the era of microprocessors as even the casual consumer became extremely literate about Megahertz and motherboards. And now, as we’ve entered the new millennium, digital signal processing (DSP) has become the technology of focus with consensus expectations of exponential growth. “Everybody knows that DSP is the technology driver for the semiconductor industry,” says Will Strauss, an analyst with Forward Concepts Co., Tempe, AZ. Why? Because semiconductors, DRAMs and microprocessors have enabled an insatiable appetite for communications in virtually every thing we do. Pervasive computing with an always-on Internet infrastructure that allows immediate access to the information that rules our business world. Voice activated controls enabled by speech synthesis to provide all members of society an equal access to the devices that can improve their quality of life. Wireless communications that keep us in touch no matter where or when we need it. A consumer industry dominated by a plethora of entertainment devices that deliver audio and video to a youthful generation with unprecedented expendable income. Guidance and navigation systems that make our transportation systems safer and more cost effective. And as the world struggles to deal with the terrorism that threatens the safety of our global societies, DSP is key to the effectiveness of the military’s command, control and communications systems. Until now, most DSP designs have been implemented in general-purpose digital signal processors from semiconductor vendors such as TI, Analog Devices and Motorola. These general-purpose processors provided an ideal implementation vehicle for DSP product development teams. General-purpose processors are relatively cheap, are supported by high quality and inexpensive programming tools, facilitate rapid implementation of DSP algorithms, and provide the flexibility development teams prefer for reprogramming during prototyping and debug. But that’s all about to change. The Need for Speed The performance requirements of today’s electronic systems now exceed the capabilities of general-purpose DSP processors. Simply put, general-purpose DSP processors are running out of gas. Figure 1 shows the projected DSP algorithm performance requirements driven by the broadband networking market versus the available performance capacity of general-purpose DSP processors over the next 3 years. The gap between the performance capacity of general-purpose DSP processors and the requirements of new broadband communication technologies widens exponentially over the next several years. The only alternative to general-purpose DSP processors previously available to DSP developers was to cast their DSP algorithms into an ASIC for hardware acceleration. An ASIC solution has proven to be less than desirable though. DSP algorithms implemented in ASICs sacrifice the flexibility of reprogrammability, command a hefty non-recurring engineering (NRE) fee, require a lengthy manufacturing cycle for initial prototypes, and mandate the purchase of expensive IC design tools. With the introduction of advanced FPGA architectures such as the Xilinx Virtex-II and the Altera Stratix-II devices, a new hardware alternative is available for DSP designers combining all the benefits of general-purpose DSP processors with the performance advantages of ASICs. These new FPGA architectures were created to optimize DSP implementations and provide the necessary computing resources to meet the performance needs of today’s electronic systems. An advantage of FPGAs is they allow the DSP designer to “fit the architecture to the algorithm” – that is, the designer can implement as many parallel resources inside the FPGA as necessary to realize the performance required of the system. In general-purpose processors, the resources are fixed as each processor contains a finite number of basic computing functions such as multiply accumulators (MAC). Thus, in a general-purpose DSP processor, the designer must “fit the algorithm to the architecture” and the required performance is not obtainable as in an FPGA.
Semiconductor Industry Bright Spot Figure 2 shows the estimated annual revenue for the total DSP market, and for the algorithm-in-silicon market subsection that includes FPGAs, structured ASICs and ASICs. The DSP algorithm-in-silicon market will grow at a compound annual growth rate (CAGR) of greater than 42% and represents one of the largest growth segments for all semiconductors in the next 3 years. The challenges that now face the DSP design community are the same ones that ASIC designers battled in the 1990s. What changes do DSP development teams need to make to their design methodologies to target FPGAs instead of general-purpose DSP processors? How do DSP design teams develop the required new design skills efficiently? How can companies afford to completely retool their design flows? How can design teams simultaneously champion a new way of implementing DSP algorithms without jeopardizing current product development schedules? And perhaps most importantly, what can managers do to minimize the risk of making decisions that could produce catastrophic results? Change needs to be managed carefully. History Repeats Itself Rapid growth in every new technology sector has required the introduction of a new design methodology to dramatically increase engineering productivity. Semiconductors flourished with the introduction of IC CAD systems by GE Calma in the late 1970s. DRAM technology exploded in the 1980s when process and transistor-level simulation tools let device physicists accurately model the behavior and manufacturing of the basic memory cell. And microprocessors, ASICs and FPGAs hallmarked the 1990s as logic designers put aside their proven schematic capture tools and took a leap of faith to top-down design flows based on logic synthesis and the Verilog and VHDL design languages. AccelChip believes the future of digital signal processing is also dependent on the adoption of a new design methodology that will allow companies to meet the DSP market’s demands in a timely and cost-effective manner. Like the ASIC and FPGA generation before, the answer for the DSP revolution is a true top-down design process.
The Way We Were DSP design has traditionally been divided into two types of activities – systems/algorithm development and hardware/software implementation. These tasks have been accomplished by two very disparate groups of engineers that often have little connection or interaction. In larger companies, it is quite common for these two groups to be physically separated with the interface between the two groups consisting of a detailed written specification that includes block diagrams, mathematical formulas and waveforms showing the expected output based upon the systems inputs. Algorithm developers create, analyze and refine the required DSP algorithms using mathematical analysis tools at the behavioral level without regard to the underlying system architecture or hardware/software implementation details. The system designer is concerned with defining the functionality and architecture of the design to adhere to the product specification and interface standards. Systems designers and algorithm developers interact efficiently with each other because they work in a common design environment based on a high-level programming language. The majority of DSP system designers and algorithm developers use the MATLAB language from The MathWorks. MATLAB has proven to provide the most productive and accurate DSP development environment because of its intuitive user interface, built-in math and graphics functions, and strong programming language. “Each time we attempted to code routines in C, we encountered subtle numerical problems and were not able to match the numerical performance of the MATLAB code,” said Jack Staub of Hughes Aircraft. MATLAB also is used extensively in universities and is often the first design language engineering students are taught, which minimizes the learning curve for companies who are continually adding new engineers to their staff. Hardware/software design teams take the specifications created by the systems engineers and algorithm developers and are tasked to create a physical implementation of the DSP design. Typically, the specification is divided into small modules and distributed to individual members of the implementation team who first must gain an understanding of the functionality of their module. If the target of the DSP algorithm is an FPGA, structured ASIC, ASIC or SOC, the first task is to create a register transfer level (RTL) model in a hardware description language (HDL) such as Verilog or VHDL. The implementation engineer is required to know communications theory and signal processing to be able to interpret the written specification provided by the systems engineer. The process of creating an RTL model and a simulation testbench usually takes about 1 to 2 months because of the need to verify the manually created RTL file exactly matches the MATLAB model. Once the RTL model and simulation environment is created, the implementation engineer interacts with the systems engineers and algorithm developers to analyze the performance, area and functionality of the hardware realization of the DSP system. It is quite common that the original algorithms and system architecture need to be modified because the systems engineers had no visibility into the physical design domain during their algorithm development. In other words, the systems engineers rely on experience, intuition and luck when they develop the system specification and as can be expected, often a good deal of refinement is required. The iteration process continues – refine the algorithms and system architecture, update the written specification, modify the RTL models and testbenches, and resimulate – until the DSP system requirements are met by the hardware realization. The implementation team then executes a standard FPGA/ASIC top-down design flow using logic synthesis to map the RTL model into a gate-level netlist and physical design tools to place and route the netlist in a given FPGA or ASIC device. Figure 3 shows the basic DSP algorithm-in-silicon design process consisting of separate design domains for algorithm development and hardware implementation. As discussed above, the lack of a link between the two design domains delays the process of design exploration until after the lengthy process of manually creating RTL models based on a written specification. Perhaps a larger concern with this design process is that the physical design of the DSP algorithms is based upon interpretation by the hardware engineers of the written specification. The lack of DSP expertise of the hardware engineers, coupled with the risk of an incomplete or ambiguous specification, often leads to catastrophic results due to misinterpretation of the required functionality. With the increase in DSP complexity, the chance of an error occurring in the manual generation of the RTL models is now the rule, no longer the exception. Thousands of man-hours are wasted doing exhaustive logic simulations to ensure the correct interpretations were made during the RTL model generation. Many times the errors are not caught in simulation because the same misinterpretations are written into the simulation testbenches, thus the hardware design errors are not found until the design reaches a prototype stage. Time is money.
One of the significant benefits that ASIC/FPGA designers realized when they moved to a true top-down design methodology was improved design data management. When ASICs and FPGAs were designed bottom-up as DSP designs are done today, many errors were introduced due to the lack of a single, golden source for the design data. In DSP design today, it is incumbent on the disparate design teams to keep their MATLAB models synchronized with the manually created RTL models and testbenches. As mentioned, these two groups have very little interaction and are usually geographically dispersed so the task of managing the design data becomes daunting. CoWare proposes a solution to the model synchronization problem in their Signal Processing Worksystem (SPW) tool suite by introducing the concept of “Simulation-Aided Design Methodology for Transition from Specification to Implementation”. In this methodology, CoWare proposes that DSP design teams create an executable specification using their Hardware Design System (HDS) with a library of DSP hardware models instead of a programming language that will allow simulation to replace interpretation of the DSP specification and algorithms. While this methodology has merits in eliminating the misinterpretations hardware engineers make in developing RTL models, it falls well short of ensuring design data synchronization. It is still the responsibility of the two disparate design organizations to manually edit their models with every modification to the executable specification, and the likelihood of errors occurring is quite high especially given the increased complexity and time to market pressures of today’s projects. A True Top-Down DSP Design Methodology AccelChip is the only company that enables a true top-down DSP design methodology for DSP algorithm developers. The AccelChip DSP synthesis tool directly reads in MATLAB models and automatically outputs synthesizable RTL models and simulation testbenches in VHDL or Verilog. By linking the two design domains of DSP, AccelChip provides DSP design teams a significant reduction in design labor and time, elimination of misinterpretations and costly design rework, automatic verification of the hardware implementation, and the ability of systems engineers and algorithm developers to perform architectural exploration in the early phases of their development cycle. Figure 4 shows a true top-down DSP design flow for FPGA implementations using AccelChip.
AccelChip eliminates the need for hardware engineers to manually create RTL models and testbenches, shaving months off the development cycle and reducing the number of engineers required to produce a hardware implementation. The RTL models that are created by AccelChip are “architecture aware” of the target FPGA device and thus are not “generic RTL” models. AccelChip uses a Resource Description Language (RDL) to provide awareness of the resources available inside each type of FPGA. When the RTL model is created, the AccelChip high-level synthesis tool will create an optimal implementation for logic synthesis, ensuring the resultant gate-level netlist takes full advantage of the FPGA device. For example, DSP algorithms implemented in one supplier’s FPGA will be significantly different in performance and area than in another’s because the architecture, logical resources and routing methodologies are different for the devices. By being architecture aware, AccelChip produces the best physical implementation for the FPGA device the DSP design team is targeting. By providing an easy to use, automated path directly from MATLAB to silicon implementation, AccelChip enables DSP systems engineers and algorithm developers to refine their algorithms early in the development cycle based on design exploration. Algorithm developers can quickly convert their MATLAB designs into a gate-level netlist for a target FPGA device to assess the tradeoffs in performance, area, cost and power. Having the feedback from the physical implementation of the algorithms early and often during the development cycle means fewer iterations are made later in the design process, again saving significant time and labor. In Summary Digital Signal Processing is one of today’s most important areas of technology development, driven by the needs of the communications, consumer, defense and transportation industries. The performance requirements of DSP algorithms are outstripping the capabilities of general-purpose DSP processors, causing DSP implementation teams to seek hardware solutions. FPGAs provide the ideal platform for DSP implementation, combining the reprogrammability, architectural flexibility, and system-level integration of general-purpose processors with the performance offered by customizable hardware. With the introduction of the AccelChip high-level synthesis tool, DSP design teams now have a tool that enables the deployment of a true top-down DSP design process. AccelChip directly links the most commonly used DSP design langugage – MATLAB – with proven HDL-based FPGA design flows, resulting in increased productivity, faster time-to-market, and improved product functionality through design space exploration early and often during the development process. AccelChip seamlessly plugs into the designer’s existing DSP environment to ensure minimal risk for management in transitioning to a true top-down DSP design methodology. AccelChip does not require the implementation of a new design language, and by providing an intuitive user interface it requires only a minimal learning curve for DSP designers. The AccelChip DSP synthesis solution allows DSP design teams to realize the full potential of their DSP algorithms in silicon. Dan Ganousis, AccelChip, Inc. March 9, 2004 About the Author: Dan Ganousis, CEO and president of AccelChip Inc., has served in executive management positions in the EDA industry for the past ten years. Prior to joining AccelChip, Ganousis served as senior vice president of Marketing and Consulting Services at Innoveda Inc. He was a key member of the management team that bought out the systems design group of Synopsys, which was previously acquired from Viewlogic Systems in 1997. Ganousis was instrumental in merging them with Summit Design, PADS Software, Omniview, and Transcendent to form Innoveda. Prior to that, Ganousis was vice president of Marketing at VeriBest, Inc., a wholly-owned subsidiary of Intergraph Corporation that sold to Mentor Graphics in 1999. Ganousis directed the creation and growth of Mentor Graphics' Professional Services organization from 1992 to 1994 as director of ASIC Design Services. Ganousis began his career as an IC Designer working at Zilog, NCR Microelectronics, Digital Equipment Corporation, and Solbourne Computer. He holds a B.S. in Electrical Engineering degree from Rensselaer Polytechnic Institute. AccelChip, Inc., 1900 McCarthy Blvd., Suite 204, Milpitas, CA 95035,
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