What’s the Right Language for DSP System-Level Design?
by Tom Feist, VP of Marketing, AccelChip

To survive our current economic climate, companies now, more than ever, need to do more with less. Recent downsizings, coupled with extreme time-to-market pressures, are forcing leading commercial, military, and aerospace companies to investigate all facets of their design process to gain that first mover advantage. To expedite development, forward looking companies are seeking solutions to augment current flows based on general purpose design languages such as C++, SystemC, VHDL, and Verilog with new flows that enable the algorithm design, chip design, and subsystem design to be verified early and often against system-level models. It is no longer sufficient to design in isolation.

This demand for greater productivity has given rise to a new set of domain-specific languages (DSLs) that promise a superior solution for system-level design. DSLs are programming languages that sacrifice generality for suitability to a particular problem area. By reducing the conceptual distance between the problem space and the language used to express the problem, programming becomes simpler, easier, and more reliable. The amount of code that must be written is dramatically reduced, increasing productivity and decreasing maintenance costs. Well architected DSLs not only provide constructs that allow concise representation of large design objects, they also come complete with visualization tools tuned for the specific design domain and provide links to the hardware and software implementation processes.

A great example of a DSL now emerging for the logic design of FPGAs and ASICs is SystemVerilog. The mission of SystemVerilog, as defined by Accellera, is “to dramatically improve productivity in the design of large gate count, IP-based, bus-intensive chips”. SystemVerilog is targeted primarily at chip implementation and verification flow, with powerful links to the system-level design flow. Based on several other DSLs, including SuperLog, Vera, OVA and PSL/Sugar, it has improvements in system-level verification capabilities over VHDL and Verilog, while maintaining an efficient path to implementation through synthesis. SystemVerilog has achieved these improvements by focusing on the problem of system-on-chip design, but it, unfortunately, does not offer these same advantages to the digital signal processing (DSP) designer.

In the DSP domain, MATLAB® is the DSL of choice with over 100,000 active users. It provides both an efficient system-level verification environment and an efficient path to implementation for standard DSP processors. Built-in abstractions liberate the designer from the strict modeling style guides that are required by general-purpose languages, allowing large design objects to be represented with a high degree of efficiency. For example, a system-level designer can represent a signal transform that can fill an entire FPGA with a single line of code, e.g., “y=FFT(x)”. MATLAB also provides a complete set of advanced graphical tools for data analysis, visualization, algorithm development, and application. However, before significant improvements in efficiency can be realized when targeting a FPGA or ASIC, a complete flow including implementation is required.

The MATLAB DSL currently provides an implementation path when the target hardware platform is a commercially available DSP processor or software running on a standard processor. Both of these implementations, however, are performance limited. High-performance DSP applications require an ASIC or FPGA as the hardware platform, but targeting these devices will sacrifice all direct paths to implementation currently provided by the MATLAB environment. This “gap” requires the DSP model to be re-implemented in a format suitable for chip design, which introduces problems into the design process such as long development cycles, human error, and reduced flexibility to make algorithm changes.

The market demand for a more efficient path from MATLAB to an ASIC or FPGA has given rise to a new breed of EDA companies such as AccelChip Inc. that bridge the gap between DSP algorithm development and silicon. AccelChip extends the capabilities of MATLAB as a DSL for chip design by automatically converting a floating-point MATLAB model to a fixed-point, synthesizable VHDL or Verilog model suitable for standard ASIC and FPGA design flows. AccelChip’s toolset enables rapid design exploration targeting fidelity, performance, area, and cost tradeoffs for optimal results while using MATLAB as a “golden source” for the downstream flow.

General-purpose languages provide adequate solutions in exchange for better integration and will continue to be used. However, with so many system suppliers now focused on achieving that next dramatic improvement in productivity, DSLs will continue to grow in popularity, and companies that use them will benefit from greater productivity, both in terms of the domain specific language and from the new breed of best-in-class tools they will enable.

Tom Feist, VP of Marketing, AccelChip, Inc.

November 18, 2003

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