Signal Processing on the Cheap
Xilinx Introduces Spartan-DSP

Xilinx might not want this article in FPGA Journal. All of us who have lived and learned in the land of LUTs are not the citizens of greatest concern for their latest announcement. We aren’t the gleam in the eye of their marketers or the glowing target in the crosshairs of their sales channel for their newest product. What Xilinx’s newly announced Spartan-DSP desires is the attention of the unannointed – the software-savvy system engineers who have long relied on digital signal processing devices to do their dirty work and who now face performance obstacles that their traditional go-to DSP devices can’t handle.

DSP with FPGAs is no longer a new idea. Folks with performance problems in areas like video and image processing have long relied on FPGAs parked next to general purpose processors or DSPs to parallelize the problem tasks and make monster problems manageable. Those people,
however, already understood the FPGA parlance. They spoke the language and were already converted to the religion. Now, with Spartan-3A DSP, the cost of entry into the realm of DSP acceleration with FPGAs is dramatically lowered, and the legions of cost-sensitive, performance-hungry applications are officially invited to join the club.

Since the beginning, low-cost FPGAs have been at least mildly competent at algorithm acceleration. FPGA vendors spent the silicon real-estate required to stack a few dozen hardware multipliers onto even the most spartan of FPGAs. The Real DSP capabilities, however, were reserved for the more expensive flagship devices. There was where one typically found the more sophisticated DSP blocks with hard-wired multiply/accumulate, enough RAM to be interesting, and I/O capable of moving masses of data around at speeds that would feed all that parallel processing power.

With Spartan-3A DSP, Xilinx has lowered the price of admission into high-performance DSP. The new family is based on the company’s well-established Spartan-3 fabric, with the added power management features of the 3A series. On top of that platform, Xilinx dropped in an array of fully-capable DSP blocks – including a great deal of potentially Virtex-cannibalizing capabilities. Xilinx heard from customers that the Virtex-class devices met a strong need in high-end applications like wireless base stations, high-definition video encoding, surveillance, broadcast, and 3D medical imaging, but more price-sensitive markets such as wireless, video, and consumer were still unserved by the most expensive high-end FPGAs. By the same token, the standard low-cost FPGA offerings didn’t have quite the capabilities that these broader, high-volume markets required to solve their signal-processing deficits.

These new markets need more than a cheap piece of silicon to meet their acceleration needs, however. The timely design of the DSP portion of these systems is a big part of the problem, and FPGAs are notoriously enigmatic for typical software-centric DSP engineers. To this end, Xilinx will lean on the years of infrastructure development investment that has, through a combination of internal and partner efforts, brought them to their current state of DSP design capability. What is that state? Well, the classic DSP programmer probably hasn’t shifted much toward FPGAs in his thinking. He still wants to code (or re-use) algorithms in C for a software-driven DSP processor. He might also model his algorithms in MATLAB to get the basic idea right before he goes to code.

If he’s more hardware-friendly, however, he may be using Simulink to assemble his algorithm from more hardware-like blocks and to quantize his data from floating point to more efficient fixed-point representations. For this forward thinker, the current state of FPGA DSP design tools offers some path to sanity. Through a variety of methods, you can start with an algorithm modeled in Simulink and get to a working hardware implementation on an FPGA without a great deal of hardware expertise. Your implementation will not be the most efficient, but you’ll usually end up with something that works acceptably.

Xilinx seems to be targeting this last class of engineer with Spartan-3A DSP. While they’d like to eventually reach the software-only folks, they’re most likely still confined to either hardware-savvy DSP dudes or the team with at least one HDL design expert on staff. Xilinx’s DSP tools are layered, including Platform Studio, SysGen, and AccelDSP as entry points. You would most likely choose one of these, depending on whether you prefer to start in Simulink or MATLAB, or whether you’re taking more of an embedded systems view of the project. The company’s standard ISE environment is used as an integration point and cockpit, and a selection of DSP-specific IP such as FFTs, FIR filters, DUC, DDCs, and CFRs are available to jump-start many common DSP projects. A selection of development boards and support tools are also available both from Xilinx and from third parties, including a $1095 Spartan-3A DSP development board that the company is already announcing.

On the silicon side, the new family features new hardware DSP blocks that rival those on the big-brother Virtex devices. The Spartan-DSP line is aligned to pick up at the bottom where Virtex-SX leaves off, offering similar DSP features but lower densities and operating frequencies and less sophisticated I/O at a much lower price point. By taking advantage of the Spartan-3A fabric, the company is also creating a family with good power-consumption characteristics, particularly when compared with the power that would be burned by enough traditional DSPs to perform equivalent work.

The family features two devices, the 3SD3400A AND the 3SD1800A, offering 126 and 84 of the new DSP48A slices respectively. The company claims that the new slices can operate at 250MHz, and, in contrast with the previous Spartan-3 multipliers, can implement many common DSP functions with little or no core LUT logic required. This translates into higher performance, greater effective logic density, and lower power consumption for DSP applications. On a benchmark like an Asymmetric FIR filter, the new family can achieve 3.3mW per 100MHz versus 5.7mW per 100MHz for regular Spartan-3.

Pricing for the new family is slotted at $29.85 USD for the 1800A device and $44.95 for the 3400A device – with the usual caveat that pricing is late 2008 at a volume of 25K units. Still – this is a much lower price point than current DSP-enhanced offerings available from the company, and the price point alone promises to land the new device in sockets in a variety of previously un-served applications.

by Kevin Morris, FPGA and Structured ASIC Journal

April 3, 2007

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