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Viewing 1 to (5 Total) Altera 28nm FPGA Preview |
Total Posts: 84
Joined: Apr 2009
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In this article (click here) we looked at Altera's plans for 28nm FPGAs. The company says they will get one up on Moore's Law with three architecture changes:
- Embedded HardCopy blocks
- 28 Gbps transceivers
- Partial reconfiguration
What do you think about these changes? Will they create substantial performance/power advantages for Altera's upcoming families, or are they marketing hy... uh, technical competitive positioning?
Posted on 2010-02-03 12:35:58 at 2010-02-03 12:35:58
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Total Posts: 21
Joined: Dec 2009
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Life, the Universe, and everything
> Please send me one Infinite Density Zero Power FPGA development kit
> and I can be set. Forever.
Infinite Density, Zero Power is where the universe started. Then it exploded and became the universe as we know it. Be careful what you ask for. We could be near the end of the cycle, our universe could be sucked into this dense FPGA mass and compressed into nothingness.
Aaaaaagggggghhh. . .
Cliff
Posted on 2010-02-03 16:50:56 at 2010-02-03 16:50:56
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Total Posts: 21
Joined: Dec 2009
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Partial
OK, that was silly.
Of the three things listed, I'm most enthusiastic about the partial reconfiguration, if they can make it work in some fairly simple way. Really, it's about LUTs, isn't it? Bigger FPGA, or some reconfigurability.
Still, it's not just the Altera part of the problem that has to be overcome, but also the software (or perhaps more FPGA code) has to be set up to handle the overlay.
I think the reconfigurability might be used in other ways to -- swapping in debugging code, error recovery, or self diagnostics when things go wrong, etc.
Cliff
Posted on 2010-02-03 16:59:29 at 2010-02-03 16:59:29
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Total Posts: 1
Joined: Nov 2009
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Partial reconfiguration is prett
Partial reconfiguration is pretty handy for telecommunication. The providers want to be able to do an upgrade to the switches and routers on a working network wihtout having to shut down. Designers turned to SW to achieve this upgradebility (not that it is easy to do in SW ...). With larger and larger FPGAs it makes more and more sense to support partial reconfiguration. A bug fix or a new feature in one engine should not cause all the others to stop. With both vendors supporting partial reconfiguration (Xilinx has had partial reconfiguration for years) I am looking forward to see this feature finally reaching high quality.
Yaron
Posted on 2010-02-04 14:56:26 at 2010-02-04 14:56:26
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Total Posts: 14
Joined: Nov 2009
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Altera Advantage
- Embedded HardCopy blocks
This sounds like they're trying to blur the divide between ASIC and FPGA. This is still unclear to me. Is the fab process the same? Or do they have a few slightly different die for combinations of hard blocks? I'm guessing the semi-custom chips the customer orders cost more than the regular ones, so it's hard to say the gain in performance is worth the extra cost.
- 28 Gbps transceivers
Considering Xilinx only boasts 11.2Gbps transceivers on their Virtex 6 chips, I'd say this banner spec is a significant advantage for Altera.
- Partial reconfiguration
This is really interesting and really opens up the possibilities. I can see this being important when doing updates and diagnostics where up-time is critical.
Posted on 2010-02-09 19:01:07 at 2010-02-09 19:01:07
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