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Viewing 1 to (7 Total) BDTi HLS Certification |
Total Posts: 84
Joined: Apr 2009
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In this feature article (click here) we looked at BDTi's new certification program for high-level synthesis tools targeting FPGAs with DSP designs. The company found that high-level synthesis delivers on its promise of high productivity design, and combined with FPGAs produces orders of magnitude better performance than DSP processor solutions with a comparable amount of engineering effort.
Do you think HLS + DSP will take over the high-end of the DSP performance spectrum?
Posted on 2010-01-20 00:18:35 at 2010-01-20 00:18:35
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Total Posts: 1
Joined: Nov 2009
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I've seen this report here and i
I've seen this report here and in EDN, and I took a look at the BDTi report also. I'm interested in HLS versus RTL but I don't see much mention of how much effort the DQPSK design took in HLS versus RTL, where effort=design+implementation+verification.
--steve
Posted on 2010-01-22 10:12:42 at 2010-01-22 10:12:42
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Total Posts: 1
Joined: Jan 2010
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Reply on Level of Effort Required
The evaluation of productivity and ease of use in the BDTI High Level Synthesis Tool Certification Program focuses on comparing a HLS-FPGA tool flow vs. a DSP processor flow. We did create a hand-coded RTL implementation of one of our applications, but this was based on an existing design, so we do not have a rigorous, first-hand analysis of the effort required. However, we did extensively use the HLS tools ourselves, and also conducted interviews with HLS tool users. Based on this, our impression is that HLS tools can produce significant savings in engineering effort compared with hand coded RTL (in the range of a 50% reduction for some users and designs). HLS tool users generally reported obtaining quality of results similar to hand coded RTL designs, and said that using an HLS tool enabled them to more easily explore alternative architectures which often led to more efficient approaches.
-Steve Ammon
BDTI
Posted on 2010-01-25 13:20:06 at 2010-01-25 13:20:06
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Total Posts: 21
Joined: Dec 2009
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Do I understand this right?
Was the comparison run between a new c->rtl (HLS) tool which is partly owned by Xilinx, and RTL version written by Xilinx personnel ? Seems like a conflict of interest which may cast doubts on the outcome.
> First, we have conclusive proof that HLS tools -- in
> the hands of regular designers -- can achieve results
> equivalent to or better than hand-optimized RTL
> written by experts.
Experts from the company that wants you to buy the HLS tools.
Don't get me wrong, I'm not suggesting collusion here. I'm not even sure I understood the test environment correctly, I'm just saying that in a scientific environment, this result would be discounted outright, wouldn't it?
Still, that aside, I think the results shown here are encouraging. The regrettable part is that VHDL or Verilog are the only development languages we can effectively compare agaist. There are better, more effective design entry techniques/languages available, but I don't think any are used widely enough to bother testing against.
> Even for an HDL expert, creating a complex algorithm
> in RTL requires easily 5x-10x the amount of work that
> it takes a software expert to develop a C or C++
> implementation of the same algorithm.
What study is this from, or is this considered a general assumption?
> If you can save even one or two months of engineering
> time getting to that RTL, it more than justifies our
> cost.
Cost justification is a tricky subject especially for tool cost in a large company. Mostly, it boils down to one project having to foot the cost for a tool several products may be able to use just because they are the first project to use it. Second, the tools budget is often a separate item from the development budget, and for a large company, this may mean that saving money in one place doesn't get you budget somewhere else. That is, you can't always get spending cash in exchange for development time or people assigned.
One final comment, I think BDTi is doing a terrific service for the industry. With tools and techniques so expensive to trial (in terms of people costs and time), it's good to have an independent organization doing some of the leg work.
Great article.
Cliff
Posted on 2010-01-26 14:44:00 at 2010-01-26 14:44:00
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Total Posts: 84
Joined: Apr 2009
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You understand it right...
Cliff -
Regarding your questions (and BDTi people might want to weigh in here as well) - My understanding is that the RTL hand-coding tests were done by Xilinx personnel - but from a completely different group than the one shepherding the HLS tests. My subjective assessment is that this does not call the data into question. If Xilinx were a finely-oiled, single-minded machine with a focused agenda, I might be suspicious. They are not. However, the RTL experts would not be serving Xilinx well if they did a sloppy job or made the RTL flow look bad, as that's the primary design mechanism used by almost all current Xilinx customers worldwide. They may want people to adopt these third-party HLS tools - but I'd bet they don't want it THAT bad.
I agree the results are encouraging. As you say - comparing VHDL and Verilog isn't the whole picture, but it covers the predominant design methods in use today for FPGAs. Also, measuring just HLS tools that start with C/C++ isn't the whole picture - there are other flows that might be considered like starting from MATLAB - particularly for DSP applications.
The 5x-10x work assumption is not based on any study - it is my assessment from my own personal experience. As you see in Steve's comment above, (if I read that correctly) BDTi's assessment was more like 50%.
Cost assessment isn't just about comparing engineering salaries (sunk cost) with tool investment. Tools that increase engineering productivity can also mean getting to market faster, beating a competitor to the punch, and increasing top-line revenue over the life-cycle of the product. In many of the markets where FPGAs are used - time-to-market is one of the critical decision factors in FPGA adoption. If HLS tools can further improve time-to-market, the cost justification becomes more compelling.
I fully agree that BDTi is providing an extremely valuable service for the industry with this process. Because of the secrecy and proprietary paranoia of EDA companies, HLS is almost impossible to evaluate objectively for the average customer. This promises to break that barrier.
Kevin
Posted on 2010-01-26 15:12:48 at 2010-01-26 15:12:48
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Total Posts: 21
Joined: Dec 2009
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In agreement
I think we're in agreement on all these points.
> Cost assessment isn't just about comparing
> engineering salaries (sunk cost) with tool
> investment.
This is true, but my point was that in the real world, sometimes you can get as many people on the project as you want, but buying a $10K piece of test equipment is right out. Different budgets. Still, I think we're saying the same thing.
Sometimes we can add 4 people for 3 months costing a couple hundred K, but can't buy a 52 inch LCD screen and sound system for showing HD DVDs\b\b\b\b\b\b\b uh ... powerpoint slides.
Cliff
Posted on 2010-01-26 15:26:31 at 2010-01-26 15:26:31
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Total Posts: 1
Joined: Feb 2010
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As an FPGA designer, I've been f
As an FPGA designer, I've been following the development of these HLS tools for some time. They seem to really be at a place now where they are useful, and not too awkward, as this article confirms. I have not used any of these high-end HLS tools myself, but in my experience with FPGA design, I have found that for many algorithms (especially image processing), one of the most complicated portions of the hardware architecture is the data movement, more than the actual algorithm. We can spend a significant portion of our development time optimizing the data movement to maximize our memory bandwidth utilization. I have always wondered how this is handled by these tools. Can anyone provide a brief summary? Thanks!
Posted on 2010-02-16 16:51:37 at 2010-02-16 16:51:37
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