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CHALK TALKPower Matters Trying to tame power consumption in your battery-powered device? Join Journal Webcasts host Amelia Dalton as she chats with Wendy Lockhart of Actel about how you can use ultra-low power programmable devices from Actel in even the most power-sensitive designs. (Actel)
CHALK TALKCreating Secure Mobile Devices With Open Kernel Labs OKL4. In this Chalk Talk, Amelia Dalton delves into the world
of software security and microkernels in mobile devices with Gernot Heiser
and Rob McCammon of Open Kernel Labs. (Open Kernel Labs)
CHALK TALK Designing Embedded Systems With Linux and low cost FPGAs. Join Amelia Dalton as she chats with industry experts about simplifying embedded systems design with Linux running on low-cost programmable system-on-chip platforms. (Xilinx)
CHALK TALK Lowest Total System Cost With Xilinx Spartan-3 Amelia Dalton chats with Mark Moran of Xilinx about reducing your overall system cost with the Xilinx Spartan-3 family of FPGAs. (Xilinx)
CHALK TALK Low Cost FPGA with Serdes Lattice ECP2M. Amelia Dalton talks with Bertrand Leigh of Lattice Semiconductor about low-cost FPGAs with multi-gigabit SerDes interface capability.
(Lattice Semiconductor)
July 1, 2008-This week, we look under the hood of the most awesomely powerful design tool in the FPGA designer’s arsenal. That’s right, we’re talking about the FAE. If we took all the FPGA projects saved by FAEs and lined them up end-to-end… everyone would understand where we’re going with this week’s newest feature article.
Also new this week, Tom Dewey of Mentor Graphics gives us tips on re-using the most valuable IP your company will ever obtain – your own. By not re-inventing the wheel with every project you can make your schedules shorter, your designs more reliable, and your job easier and more fun.
Thanks for reading! If there's anything we can do to make ourpublications more useful to you, please let us know at:comments@fpgajournal.com. If you'd rather sound off in public, please post your comments or questions in our new Journal Forums.
Kevin Morris – Editor in Chief
Techfocus Media, Inc.
Renaissance FAEs
Our Once and Future Saviors
(Kevin Morris)
In classical music, they are the organists.
My brother, an accomplished professional trumpet player, had just completed a performance for solo piccolo trumpet and organ. I was looking at his immaculately maintained instrument and noticed that one of the tuning slides was so light, it seemed it could just fall off the horn if the performer held it at the wrong angle.
“What would you do if this fell off during a performance?” I asked.
Seemingly without thinking, he replied “Oh, the organist would catch it and replace it.”
I was briefly puzzled.
“Yes,” he continued, “She’d catch it and put it back – tuned exactly right - while simultaneously sight-reading five lines of music at different tempos and in different keys, playing with both hands and both feet, painting her nails… and playing jacks to keep herself from getting bored.”
Building an FPGA Design Repository by Tom Dewey,
Mentor Graphics Corporation
How often has it happened that you have just finished a complex module for an FPGA project only to later find out that a very similar module was completed a month earlier by another team within the company? Not only have you just wasted several weeks of your time, but this wasted time has also cost the company money. A quick way to become a hero by saving the company both time and money is to put in place a simple reuse repository to prevent this scenario from ever happening again.
Today many design teams and companies are considering putting a reuse repository infrastructure together. The main benefits of a reuse repository are:
Preventing wasted time due to creating designs blocks that already exist.
Completing projects faster by leveraging existing design blocks in new designs.
Concentrating the team’s creative skills on new design aspects of a project rather on recreating the wheel. [more]
Two Chips Or One? Avnet Provides a Daughter-card SERDES Solution for Spartan
(Bryon Moyer)
A few years ago when SERDES became available on FPGAs, they were exotic. Both for the FPGA guys and for their users. The FPGA guys had to learn how all this stuff worked, tune the (relatively) complicated analog circuits, and make it all function. Those were some of the last features to be officially released on those devices because they just took longer to get right. More than one customer was stranded waiting for parts with working high-speed I/Os.
Meanwhile, there weren’t a lot of customers who knew what to do with this stuff. The protocols were complex, and rolling your own took fortitude. And likely a stiff drink to steady the nerves. They looked to the FPGA guys for help, and the FPGA guys were looking to them for help. Gradually the FPGA guys got a handle on things and even defined their own lightweight high-speed serial protocols – Aurora for Xilinx and SerialLite for Altera. But the FPGA guys were scared to death of what customers might try to do – this collection of circuits could be put together in all kinds of scary demonic ways that may or may not have been intended. So they tried to limit the ways in which they could be used – essentially defining “sandboxes” in which customers could play. Go outside the sandbox, and you’re on your own – no support.
[more]
A Passel of Processors
NVIDIA’s Tesla T10P Blurs Some Lines (Kevin Morris)
Picture this architecture – a high speed application processor doing control coupled to an accelerator comprised of a mass of processing elements ready to power-parallelize compute-intensive components of a complex problem. Sound familiar? Supercomputers have taken advantage of acceleration using schemes like this for a while. People using FPGAs for co-processors do it all the time.
Now, picture a new chip with 1.4 billion transistors, an array of 240 cores, and a processing throughput equivalent to about 1 TeraFLOPS. Many readers of this publication would probably guess a new FPGA, right? [more]
Employing an I/O Interlocutor FMCs Decouple FPGAs from Complex I/Os (Bryon Moyer)
It used to be so simple. PLDs provided a medium by which you could create and modify logic without having to make any board changes. All the variability was on the inside; the outside consisted of I/Os, and, back in the day, that meant one thing: TTL. Eventually, when CMOS became more prevalent, the less-often-used rail-to-rail CMOS interface was available, but those I/Os were on different devices that were dedicated to the CMOS low-power market.
[more]
Xilinx speeds HDL simulation with SecureIP and FAST Simulation Mode Models by Howard Walker,
Xilinx, Inc.
Xilinx Virtex-class FPGAs feature several advanced hardwired, hard IP blocks, some of which we must protect for legal reasons. Traditionally, to allow customers to use these blocks effectively while preventing theft or tampering, we’ve offered customers black-box simulation models called SmartModels of these cores. However, some customers have found these models hard to use and note the models tend to run much slower than regular RTL models in third-party simulation environments. So with the introduction of Virtex-5 FPGAs, we now support a much faster, easier to use but protected form of simulation model called a SecureIP model. [more]
New Kid in Class
SiliconBlue Debuts Low-Power FPGAs (Kevin Morris)
There’s a new kid in class.
We’ve all been through this scenario before. All the players are comfortable in their established roles. The leader tries to stay ahead and always communicates with the purpose of maintaining the perception of leadership. The second player vies constantly with the leader for supremacy and mind-share, always trying to one-up the alpha dog. The third through fifth players are constantly flanking, trying to differentiate and establish themselves based on supremacy in a particular niche.
[more]
Not Bad Die Xilinx EasyPath Explained
(Kevin Morris)
We always thought we knew how it would go down.
Under cover of darkness, our black-clad insertion team would rappel down the walls of the super-secret Xilinx fortress in the desert. With the kind of precision timing and teamwork found only in movies and editorial feature introductions, we’d scan the perimeter and locate the vulnerable point. A diamond-tipped drill bit driven by a silent motor would bore a hole just large enough for our fiber-optic viewing tool, and the telling video would be immediately beamed back to FPGA Journal headquarters. At the same time, however, we’d inadvertently trigger the alarm system, and our squad would fragment, running for cover. In a panic, our leader would end up like Charlton Heston, running for his life through the streets shouting, “EasyPath is Bad Die! EasyPath is Bad Die!”
Avoid FPGA Project Delays by Adopting Advanced Design Methodologies by Alex Vals, Mentor Graphics
Introduction
Over two-fifths of FPGA design projects fall behind schedule. In order to reduce risk of delay of product delivery, changes need to be made not just in verification and production but also in the design process. Design simplification must be a principle that starts at the beginning of the project life cycle – before verification of complex code has become the bottleneck that delays project delivery. [more]
40nm Altera Stratix IV Bigger and Cooler than we Expected
(Kevin Morris)
New process nodes have a predictable rhythm. Until about 90nm, we knew before anybody announced anything that we’d get double the density, half the power (dynamic, of course), and 50% more speed than we had in the previous generation. Of course, that made waiting for the announcements from semiconductor companies a little less than suspenseful. Our Moore’s Law alarm clock would beep on its two-year cycle. We’d check to see if anybody had announced the thing we were expecting yet, and then we’d hit the one-month snooze button and fade back off into our dazed delirium. [more]
