Packing Processor Power
Altera Introduces Nios II

Attention please! The days when embedded soft-core processors on FPGAs were novel little micro-controllers you could use instead of a hard-wired state machine are now officially over. Thank you.

You could use Altera’s new Nios II processor as a convenient replacement for a hard-wired state machine in your next FPGA design. You could also play Pong on your Pentium 4. In both cases, you’d be missing the point and serious under-utilizing your processor technology.

This week, Altera announced the long-anticipated sequel to their popular Nios soft-core processor, and it is quite impressive. In short: Speed, flexibility and capability – up, size and cost – down. If you’re a hardware designer, you may puzzle at the soft-core concept. Wouldn’t hard-wired processors work better in the same way that hard-wired multipliers do? If you think that, bookmark this page, walk across the hall, and have a discussion with an embedded software developer. (They’re really quite approachable and some of them even keep candy on their desks.)

In case you couldn’t locate a software engineer, here’s a brief rundown. First, you only use a processor when you want it, and the FPGA vendor doesn’t have to make the device more expensive by including hard-core processors that many customers will not need. Second, you only need to use enough resources to make the particular processor you need for your application. The new Nios-II family ranges from an “economy” version that consumes a miserly 500 logic elements (less than 20% of a low-cost Cyclone device), to a “fast” version (rated at over 200DMIPS on a Stratix II FPGA) that requires just over a thousand. Third, you can configure the processor to have just the special features you need without paying for what you don’t need. With configurable caches, custom instructions and varying pipeline depths you can create a processor that is perfectly suited to your application. Finally, it may not be a question of which processor to use, but how many. With a 220DMIPS (fast) Nios II CPU requiring only 1% of a large Stratix II device, you can pile them on your FPGA like parmesan on pizza.

It would be easy to evaluate Nios II in a vacuum, but failing to look at the bigger picture would sell short the potential of this powerful processing environment. In the larger context of FPGA-based reconfigurable computing, you can use parallel processing, custom instructions and hardware acceleration to push the performance of this platform into the stratosphere. For some applications, the combination of parallel Nios IIs running algorithms and control with hardware acceleration of math-intensive datapath processes (leveraging the built-in hardware multiply/accumulate resources of Stratix II) could drive your DMIPS off the map. [more]

The Next Implementation Fabric: Issues and Considerations
by Andrew B. Kahng, Technical Program Co-Chair for Design Tools, 41st Design Automation Conference, Professor of CSE and ECE at the University of California, San Diego

The semiconductor industry is caught on two horns of the economics dilemma:

-- Technology scaling – sub-wavelength lithography, masks, and variability; and

-- Design productivity – turnaround time, and reusability of design effort.

Proliferation of semiconductors and their applications benefits from fast, cheap, and under-control ASIC-style implementation. Thus, the industry needs one or more implementation fabrics that support medium volume, lower cost, power and nonrecurring engineering (NRE) costs. To this end, several semiconductor technologies offer different visions of the next implementation fabric, as well as the application domains or cost-performance tradeoff points that such a fabric must support.

On one end of the flexibility spectrum, FPGA vendors offer programmable ICs with highly regular switching and logic fabrics; these offer designers near-zero NRE costs, low design costs and fast turnaround times. The tradeoff is that FPGA fabrics incur higher unit costs, lower integration densities and operating frequencies, and increased power dissipation. [more]