Pedal to the Metals
A Crash Course in High-Speed Design

You're cruising home from work one day, and your cell phone rings. You answer (hands free of course...). It's your boss. New plan. He’s saying something about routing, but you can’t quite make it out. Your head is spinning. Why didn't you pay the extra thousand bucks for that GPS system? Your boss is still talking, and you're trying to make sense of what he's saying, but it's all rushing together, plus you've reached that "Can you hear me now" section of your commute. You catch a word here and there, but it's gibberish. Things like, "... Microvia." Sounds like a small island in the South Pacific, but OK. Then something about constrained nets. Is this some kind of code speak for a speed trap ahead? Well, sort of. In reality, you’ve just been assigned the task of designing your first FPGA-centric high-speed board.

Times have changed since ASICs ruled the board. With an FPGA in the middle of the system, board design has become part of the "on-demand" culture. Pinouts aren’t nailed down months in advance the way they used to be. They can change right up until the last minute. You could be dealing with more than 20 layers of metal. You’ve got high-speed serial signals to deal with. You’ll need routing constraints for the majority of these. And let’s not forget the old stand-bys, the bread-and-butter challenges of high-speed design: signal integrity, jitter, and crosstalk. [more]

Selecting the FPGA that Meets Your Signal Integrity Requirements
by Lalitha Oruganti, Sr. Product Marketing Engineer, FPGA Products, Altera Corporation

In light of its critical nature, signal integrity needs to be a key criterion during the planning and design phases of high-speed systems. Ignoring signal integrity can lead to poor reliability, degraded performance, field failures and delayed product releases—all of which can trigger lost opportunities and revenues.

Today’s high-end FPGAs support a variety of single-ended and differential I/O standards, with options to control drive-strength, slew-rate and on-chip termination. If not used correctly, this flexibility offered by FPGAs can make it difficult to manage signal integrity. Selecting the right FPGA that meets specific signal integrity requirements is critical for individual design success. Evaluating FPGAs requires a thorough understanding of the design methodology and features available in the FPGA to manage signal integrity, models and characterization data. This article will outline the specific information required of FPGA vendors before selecting the right device for a specific high-speed design. [more]

ANNOUNCEMENTS ModelSim Designer – Free 30 Day Evaluation A Windows®-based design environment for FPGA simulation with a built-in design creation engine. We could go on and on telling you how great ModelSim Designer is, but there’s really only one way to find out – try it for yourself. Download your evaluation copy now--it's free! Free Online Seminar - Verify your Embedded FPGA Design. Watch this short presentation to learn how FPGA designers gain better controllability, observeability, and architectural exploration to meet the critical system performance and cost pressures. Within the Seamless co-verification environment, Xilinx designers can take advantage of the unique software and hardware programmability of the Xilinx Virtex-II Pro FPGAs, with the embedded PowerPC 405 processor. Co-Verification reduces overall design effort because it is faster than logic simulation, provides exceptional debug compared to a prototype, and enables performance analysis. Find a better job. Browse FPGA Journal’s new job listings to find challenging and rewarding opportunities with the FPGA industry’s top companies. Journal Jobs is specifically for FPGA professionals – more of what you’re looking for, less of what you’re not. Browse now! Hire the best FPGA talent in the industry with FPGA Journal Job Listings. Starting this month you can reach 30,000 active FPGA professionals by advertising your FPGA-related positions in Journal Jobs. Click here for info.