The continuing evolution of field programmable gate arrays (FPGA) has enabled design teams to develop larger and more complex designs. The increases in design size and complexity are enabled in part by CPUs and other cores that are not developed in-house. The broad availability of these rich resources places greater demands on design and verification teams.

The flexibility to use bigger and faster FPGAs also strains the capabilities of design creation, simulation, synthesis, and place-and-route tools. Each design start may require unique tool resources, placing a premium on the ability to change and adopt new tools in your flow. Changes can be influenced by many factors. For example, the required IP may be in a different HDL language; the chosen IP may be supported by a specific subset of tools; or a new verification language may be introduced into your methodology.

The time has come for a new class of design methods and tools that enable more thorough design entry, simulation, and implementation, as well as the management of these tasks. Ideally, the comprehensive process of FPGA design creation to realization should be managed from a single, flexible user interface, enabling a seamless design and verification flow for significant productivity gains. [MORE]

Innovations in field programmable gate array (FPGA) architecture and the move to 90-nm process technologies have delivered a dramatic increase in both FPGA density and performance. Besides higher logic densities and faster performance, FPGA designers demand more complex device features such as embedded memory, digital signal processing (DSP) blocks and other hard IP structures. However, as FPGA designs have become larger and more complex, designers have less time to complete their designs before their market opportunity vanishes.

FPGA device vendors have been trying to keep up with improvements in compilation time efficiency and timing closure flows. Unfortunately, these improvements have not kept pace with the need for increased designer productivity. Altera’s Quartus® II software version 5.0 incremental compilation technology delivers that productivity improvement by offering dramatically shorter design iteration times and unprecedented ability to target design optimizations to critical performance paths and preserve performance in areas where performance requirements are already satisfactory. [MORE]

Overview
DSP systems are often best described using a combination of graphical and language-based methods. The MathWorks, the industry leader in DSP modeling software, caters to this dichotomy by providing a cycle-accurate graphical design environment called Simulink® and a mathematical modeling language called MATLAB®. Simulink is well suited for the "system" aspects of DSP design, including control and synchronization of data flow to and from interfaces and memories. Simulink also provides a rich set of pre-defined DSP algorithms in the form of "blocksets" from which DSP systems can be constructed. Simulink is not, however, the most effective environment for modeling proprietary algorithms. It unnecessarily burdens the designer with cycle-accurate considerations and forces low-level arithmetic operations and array accesses to be constructed from graphical blocksets rather then concise, textual expressions.

DSP algorithm developers have found that the MATLAB language best meets their preferred style of development. With more than 1000 built-in functions, as well as "toolbox" extensions for signal processing, communications, wavelet processing, etc., MATLAB offers a rich and easy-to-use environment for the development and debugging of sophisticated algorithms. Simulink 6.0 unifies these two modeling environments with the "Embedded MATLAB Block" that allows MATLAB models to simulate within Simulink and compile into C-code through Real-Time Workshop® for processor-based DSP hardware implementations. [MORE]

It is apparent to the most casual observer that FPGAs are increasingly becoming viable candidates for many SoC applications. The introduction of true million plus system gate FPGA products, along with a plethora of IP options, both hard and soft, have made FPGAs the platform to beat for all but the highest performance or volume designs. The flip side of this high performance capability is that FPGA designs now have levels of complexity on par with many SoCs, but often without the time, budget, or resources traditionally associated with SoC verification.

For many typical system FPGA applications, silicon verification must address the run control and in-system analysis of embedded processors, their coordinated operation with the larger numbers and complexities of secondary application specific cores, and buses that provide on-chip communication. System analysis considerations include both the initial concerns of whether everything is designed in correctly, and later concerns of identifying, understanding and optimizing performance related issues. These issues can include processor code debug and tweaking, as well as core to core communication efficiency, latency, conflicts, etc. that have a direct impact on system operation. [MORE]

Introduction
ASIC designs continue to increase in size, complexity, and cost. (For the purpose of these discussions, the term ASIC is assumed to encompass ASSP and SoC devices.) At the same time, aggressive competition makes today's electronics markets extremely sensitive to time-to-market pressures. Furthermore, market windows are continually narrowing; in the case of consumer markets, for example, a “typical” ASIC design cycle is in the order of 12 to 24 months, while the window of opportunity for the introduction of a product using this device can be as little as two to four months.

Failing to have a product available at the beginning of the intended market window may result in significantly reduced revenue (or a complete loss of revenue and investment if the window is missed in its entirety). These factors have dramatically increased the pressure for ASIC designs to be “right-first-time” with no re-spins. In turn, this has driven the demand for fast, efficient, and cost-effective verification at both the chip and system levels.

In the case of a modern ASIC design, a software simulation running on a really high-end (and correspondingly expensive) computer platform will be lucky to achieve equivalent simulation speeds of more than a few Hz (that is, a few cycles of the main system clock for each second in real time). Practically, this means that detailed software simulations can be performed on only small portions of the design. [MORE]

The Unmet Demand For Low-Cost, Non-Volatile FPGAs

Although SRAM FPGAs dominate the FPGA market, the vast majority of designers would prefer a non-volatile, reprogrammable FPGA solution -- provided the associated cost premium is not too great. This is illustrated in Figure 1, which summarizes the results of a Lattice Semiconductor survey of FPGA designers. Their desire for a nonvolatile
solution is driven by multiple factors, including the need for:

• Smaller board area and the simplicity of a single-chip solution
• Rapid availability of logic after power-up
• Higher security than is possible with traditional FPGAs
• Real time reprogrammability

LatticeXP (eXpanded Programmability) FPGAs deliver the benefits of non-volatility at an economical price point. This has been achieved by combining a low-cost 130nm embedded FLASH technology with the optimized FPGA architecture found in LatticeEC (EConomy) FPGAs. This combination has enabled Lattice to reduce the die size over 80% between its first generation non-volatile FPGAs and the LatticeXP devices. This is illustrated in Figure 2. [MORE]