Death of the Hardware Engineer
A Dirge for the Digital Designer

Exactly two hundred years ago this June, Augustus De Morgan was born. Arguably, before that time, there were no logic designers in the world. For the next 200 years, however, logic designers steadily increased in number until today, when we walk the earth in six or seven digit numbers. In the big picture, however, the time for our species may be drawing to a close. Self-made storm clouds have been on the horizon for awhile now, the engineer-extincting meteors are headed for earth, and the distant dirge of death for the digital design profession as we know it grows ever-louder over the horizon.

Any engineering discipline done well should ultimately be self-eradicating. The key problems should be solved from the bottom up, and the creative genius of each generation should be absorbed into the collective tooling, IP, and best-practice methodologies of the next. Today, digital design bears little resemblance to what I learned in school twenty something years ago. For many of today's bright young engineers, DeMorgan equivalents are something they learned in an introductory logic design class, but not anything they apply in their day-to-day work. They're much more likely to be worried about whether the Ethernet stack they are dropping into the software side of their system is compatible with the version of the MAC they bought from their silicon IP supplier, whether the layout will meet timing without some manual tweaking to the chip layout, and if electro migration will cause a reliability problem in their 90nm-based technology at the junction temperatures they're likely to be running.
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Need to Accelerate the Creation of Technology-Independent DSP Hardware?
by Shawn McCloud, Mentor Graphics

The massive increase in processing required for next generation compute-intensive applications, such as wireless communication and image processing, has created a gap between off-the-shelf DSP performance and market needs. In many cases, discrete DSPs are simply running out of steam to serve the new communications, multimedia, and consumer applications. In recent years, users have increasingly looked toward alternative solutions ranging from ultra-high performance full-custom ASICs to highly flexible general-purpose CPUs. Somewhere in the middle are FPGAs, providing a cost-effective balance (Figure 1) between programmability and high performance. With their processing flexibility ranging from serial to parallel computing, and now containing highly specialized DSP macros and memories, FPGAs have the potential to become an attractive option in which to implement DSP algorithms.

Each platform has certain benefits and limitations. On one extreme, the pure software approach implemented in discrete DSPs is mature, flexible, and relatively easy to use but offers limited instruction-level parallelism. On the other extreme, ASIC implementations offer custom performance and high volume pricing benefits but traditionally constitute a much greater design effort and soaring NRE costs. Demonstrating some of the value from both extremes, FPGA hardware supports reprogrammability and architecture flexibility in terms of spatial and temporal parallelism (via repetition and pipelining) but lacks ease of programming since design entry is in a register-transfer level (RTL) hardware description language versus the DSP program domain of ANSI C/C++. [more]