Blaming the Button
Physical Synthesis Moves to Mainstream

We FPGA designers work hard to get our RTL ready to rumble. We round up our IP, mull over the microarchitecture, sweat over the simulation, and finally get things lined up well enough to push the big GO buttons for synthesis and place-and-route. After that, the design is mostly out of our hands, right? The tools do their job, and, unless we have some critical paths that need optimizing, some LUTs hanging around loose after placement, or some routes that ended up unrouted, we just sit back and wait for the system to tell us that everything is hunky-dory. When the A-OK signal comes back, we grab our new bitstream and head off to programming paradise, unaware that we may have just left staggering quantities of design excellence on the table.

How staggering? According to a recent paper published by Jason Cong and Kirill Minkovich of UCLA, the optimality of logic design alone can be off by as much as 70-500X. That's not a percent sign, boys and girls; that big X means that your design may be taking up 70 to 500 times as many LUTs as the best possible solution. The UCLA study compared synthesis results from academic and commercial synthesis tools with known-optimal solutions for a variety of circuits. The paper says that the synthesis tools were 70 times larger in area on average than the known optimal solutions in the test study.

While these examples are admittedly academic, and real-world designs may not suffer as badly, this is still a staggering difference. Area is only one part of the story, however, and many of the timing optimization techniques employed by modern synthesis tools involve replicating logic to improve timing. That kind of behavior is not going to help the area score much. Many times, if the tool had done a better job of logic minimization initially, the subsequent replications would not have been necessary. They're often attempted make-ups for having too many levels of logic in the first place.

Area woes aside, there's an even bigger design demon arising that threatens to dwarf the suboptimal synthesis problem. As geometries continue to press smaller – with some FPGA companies now talking about 65nm products, the contribution of routing and interconnect as an overall percentage of the delay in any given path is increasing. This contribution is already large enough that routing, rather than logic, is the dominant factor in delay on most real paths. [more]

Innovation Big and Small
Chapter 1 - The Adventures of Chuck & Roger

It's four o'clock in the morning. Roger gets up from his laptop to walk to the dorm-size refrigerator in the corner of the makeshift office. He pulls out a Mountain Dew, downs a sizable swig, and then places the can at the end of a row of six empties that have accumulated beside his keyboard during the evening. Adjacent to his desk sits a pyramid of empty Mountain Dew cans – an art project in progress, a monument to a month of Roger's late-night work-a-thons, all aimed at getting the product ready for tomorrow's big customer demo. Beyond the Dewamid lies a sleeping bag containing Roger's office mate. He had lasted until 2AM when he kicked off his own regression test run and then crawled in for a nap. Roger has instructions to watch the job and wake him if it finishes.

Caffeine, cold liquid, and carbonation re-open Roger's sagging eyes. His monitor locks back into sharp focus again. His latest unit test run will be done within a couple of minutes. If it passes, he'll check in the files, kick off a build, and head home for two or three hours of real bed rest before trying to make himself look semi-professional for the presentation at 9AM. He doesn't want to be too slick. People expect a lead engineer at a startup to have a certain patina.

If the demo goes well and the customer issues a PO, it will provide the real-world validation that the venture capitalists are looking for in order to proceed with the third round of funding. The funding is key. Without it, the company will close down within weeks. With it, they'll have the resources they need to bring the product to market. Roger is confident that, if that happens, the company will be acquired at a premium within two years. He'll be set to retire at 26. Roger's wife of two years sleeps soundly alone at home. She hasn't had more than an hour alone with her husband in over a month, but she's patient with the temporary hardship. She understands what this means for their future.

Five and a half hours later, at nine-thirty, while Roger is starting his make-or-break demonstration, wearing his blue blazer over a polo shirt with jeans and converse sneakers, another engineering deadline is approaching. In the next building over, home to a product development team from a multi-billion-dollar public corporation, Chuck is running late for work. His oldest daughter toddles after him down the hallway toward the day-care center, teddy bear in tow. Chuck mentally blames the company for his tardiness. If they'd expanded the day care facility like they'd promised a year ago, he wouldn't have to drop his youngest kid off at the other place every morning until his day care spot came up on the waiting list. Chuck swings past the company fitness center and slots his name in for racquetball at noon. He can play for an hour, shower, and still get to the cafeteria before they stop serving at one-thirty. He'll be done with lunch by two fifteen and back at his desk in time for his two thirty weekly program review meeting.
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