CURRENT FEATURE ARTICLES

Employing an I/O Interlocutor
FMCs Decouple FPGAs from Complex I/Os
(Bryon Moyer)
Performance Improvements with New Secure IP and FAST Simulation Mode Models
by Howard Walker, Xilinx, Inc.
New Kid in Class
SiliconBlue Debuts Low-Power FPGAs (Kevin Morris)
Not Bad Die
Xilinx EasyPath Explained (Kevin Morris)
Avoid FPGA Project Delays by Adopting Advanced Design Methodologies
by Alex Vals, Mentor Graphics
40nm Altera Stratix IV
Bigger and Cooler than we Expected (Kevin Morris)

JOURNAL WEBCASTS

NEW!! CHALK TALK Power Matters. Trying to tame power consumption in your battery-powered device? Join Journal Webcasts host Amelia Dalton as she chats with Wendy Lockhart of Actel about how you can use ultra-low power programmable devices from Actel in even the most power-sensitive designs. (Actel)

CHALK TALK Creating Secure Mobile Devices With Open Kernel Labs OKL4. In this Chalk Talk, Amelia Dalton delves into the world of software security and microkernels in mobile devices with Gernot Heiser and Rob McCammon of Open Kernel Labs. (Open Kernel Labs)

CHALK TALK Low Power Design With Xilinx and Linear Technology. Join Amelia Dalton as she chats with Mark Moran of Xilinx and Afshin Odabaee of Linear Technology about low power FPGA based designs. (Xilinx)

CHALK TALK Designing Embedded Systems With Linux and low cost FPGAs. Join Amelia Dalton as she chats with industry experts about simplifying embedded systems design with Linux running on low-cost programmable system-on-chip platforms. (Xilinx)

CHALK TALK Lowest Total System Cost With Xilinx
Spartan-3. Amelia Dalton chats with Mark Moran of Xilinx about reducing your overall system cost with Xilinx Spartan-3 family of FPGAs (Xilinx)

CHALK TALK Low Cost FPGA with Serdes Lattice ECP2M. Amelia Dalton talks with Bertrand Leigh of Lattice Semiconductor about low-cost FPGAs with multi-gigabit SerDes interface capability. (Lattice Semiconductor)

[click here for more webcasts]

Employing an I/O Interlocutor
FMCs Decouple FPGAs from Complex I/Os
(Bryon Moyer)

It used to be so simple. PLDs provided a medium by which you could create and modify logic without having to make any board changes. All the variability was on the inside; the outside consisted of I/Os, and, back in the day, that meant one thing: TTL. Eventually, when CMOS became more prevalent, the less-often-used rail-to-rail CMOS interface was available, but those I/Os were on different devices that were dedicated to the CMOS low-power market.

Well, the first hints that the age of innocence was coming to an end appeared with the lowering of the power supply voltage from 5 V to 3.3 V. This was mostly managed through more careful I/O design so that, if possible, a 3.3-V I/O could tolerate 5-V signals when it was connecting to a device that was still on a 5-V supply. Yeah… remember when we scratched our heads wondering how one would manage two – count them, TWO! – supplies on a board? No longer could we ignore the I/O and simply focus changes on the internals of the PLD. The I/O now became part of the design work. [more]

Xilinx speeds HDL simulation with SecureIP and FAST Simulation Mode Models
by Howard Walker, Xilinx, Inc.

Xilinx Virtex-class FPGAs feature several advanced hardwired, hard IP blocks, some of which we must protect for legal reasons. Traditionally, to allow customers to use these blocks effectively while preventing theft or tampering, we’ve offered customers black-box simulation models called SmartModels of these cores. However, some customers have found these models hard to use and note the models tend to run much slower than regular RTL models in third-party simulation environments. So with the introduction of Virtex-5 FPGAs, we now support a much faster, easier to use but protected form of simulation model called a SecureIP model.

These new models have significant ease of use and performance advantages over SmartModels but there are some differences users should become familiar with to use the SecureIP models very effectively. [more]