CURRENT FEATURE ARTICLES

A Passel of Processors
NVIDIA’s Tesla T10P Blurs Some Lines
(Kevin Morris)
Employing an I/O Interlocutor
FMCs Decouple FPGAs from Complex I/Os
(Bryon Moyer)
Performance Improvements with New Secure IP and FAST Simulation Mode Models
by Howard Walker, Xilinx, Inc.
New Kid in Class
SiliconBlue Debuts Low-Power FPGAs (Kevin Morris)
Not Bad Die
Xilinx EasyPath Explained (Kevin Morris)

JOURNAL WEBCASTS

CHALK TALK Power Matters. Trying to tame power consumption in your battery-powered device? Join Journal Webcasts host Amelia Dalton as she chats with Wendy Lockhart of Actel about how you can use ultra-low power programmable devices from Actel in even the most power-sensitive designs. (Actel)

CHALK TALK Creating Secure Mobile Devices With Open Kernel Labs OKL4. In this Chalk Talk, Amelia Dalton delves into the world of software security and microkernels in mobile devices with Gernot Heiser and Rob McCammon of Open Kernel Labs. (Open Kernel Labs)

CHALK TALK Low Power Design With Xilinx and Linear Technology. Join Amelia Dalton as she chats with Mark Moran of Xilinx and Afshin Odabaee of Linear Technology about low power FPGA based designs. (Xilinx)

CHALK TALK Designing Embedded Systems With Linux and low cost FPGAs. Join Amelia Dalton as she chats with industry experts about simplifying embedded systems design with Linux running on low-cost programmable system-on-chip platforms. (Xilinx)

CHALK TALK Lowest Total System Cost With Xilinx
Spartan-3. Amelia Dalton chats with Mark Moran of Xilinx about reducing your overall system cost with Xilinx Spartan-3 family of FPGAs (Xilinx)

CHALK TALK Low Cost FPGA with Serdes Lattice ECP2M. Amelia Dalton talks with Bertrand Leigh of Lattice Semiconductor about low-cost FPGAs with multi-gigabit SerDes interface capability. (Lattice Semiconductor)

[click here for more webcasts]

A Passel of Processors
NVIDIA’s Tesla T10P Blurs Some Lines
(Kevin Morris)

Picture this architecture – a high speed application processor doing control coupled to an accelerator comprised of a mass of processing elements ready to power-parallelize compute-intensive components of a complex problem.  Sound familiar?  Supercomputers have taken advantage of acceleration using schemes like this for a while.  People using FPGAs for co-processors do it all the time.

Now, picture a new chip with 1.4 billion transistors, an array of 240 cores, and a processing throughput equivalent to about 1 TeraFLOPS.  Many readers of this publication would probably guess a new FPGA, right? 

With the new Tesla T10P GPU, NVIDIA is making a lot of us editors re-work our glossaries.  The T10P is a GPU that’s aimed directly at the high-performance computing community, not just accidentally clipping it with a bank shot while going after the real target market of graphics acceleration.  The T10P represents NVIDIA’s second generation of CUDA (Compute Unified Device Architecture) GPUs (with the Tesla 8 being the first).  CUDA is a C dialect with specific constructs for parallelism, and it allows direct access to the low-level hardware capabilities of the processor cores of the GPU.  Why would we want that?  To do non-graphics applications, of course. 

You see – unless your performance-critical application happens to involve a lot of shading and texture mapping, GPUs have traditionally been a locked treasure chest, not ready to share all that parallel-processing goodness with those who aren’t trying to blast billions of bits onto a screen.  Many people have always known that processing power was in there, though, and an access mechanism like CUDA is the key that lets them get in to put all those processors to work - doing a lot of interesting tasks that are most certainly NOT graphics acceleration. [more]