CURRENT FEATURE ARTICLES

Two Chips Or One?
Avnet Provides a Daughter-card SERDES Solution for Spartan (Bryon Moyer)
A Passel of Processors
NVIDIA’s Tesla T10P Blurs Some Lines
(Kevin Morris)
Employing an I/O Interlocutor
FMCs Decouple FPGAs from Complex I/Os
(Bryon Moyer)
Performance Improvements with New Secure IP and FAST Simulation Mode Models
by Howard Walker, Xilinx, Inc.
New Kid in Class
SiliconBlue Debuts Low-Power FPGAs (Kevin Morris)
Not Bad Die
Xilinx EasyPath Explained (Kevin Morris)

JOURNAL WEBCASTS

CHALK TALK Power Matters. Trying to tame power consumption in your battery-powered device? Join Journal Webcasts host Amelia Dalton as she chats with Wendy Lockhart of Actel about how you can use ultra-low power programmable devices from Actel in even the most power-sensitive designs. (Actel)

CHALK TALK Creating Secure Mobile Devices With Open Kernel Labs OKL4. In this Chalk Talk, Amelia Dalton delves into the world of software security and microkernels in mobile devices with Gernot Heiser and Rob McCammon of Open Kernel Labs. (Open Kernel Labs)

CHALK TALK Low Power Design With Xilinx and Linear Technology. Join Amelia Dalton as she chats with Mark Moran of Xilinx and Afshin Odabaee of Linear Technology about low power FPGA based designs. (Xilinx)

CHALK TALK Designing Embedded Systems With Linux and low cost FPGAs. Join Amelia Dalton as she chats with industry experts about simplifying embedded systems design with Linux running on low-cost programmable system-on-chip platforms. (Xilinx)

CHALK TALK Lowest Total System Cost With Xilinx
Spartan-3. Amelia Dalton chats with Mark Moran of Xilinx about reducing your overall system cost with Xilinx Spartan-3 family of FPGAs (Xilinx)

CHALK TALK Low Cost FPGA with Serdes Lattice ECP2M. Amelia Dalton talks with Bertrand Leigh of Lattice Semiconductor about low-cost FPGAs with multi-gigabit SerDes interface capability. (Lattice Semiconductor)

[click here for more webcasts]

Two Chips Or One?
Avnet Provides a Daughter-card SERDES Solution for Spartan
(Bryon Moyer)

A few years ago when SERDES became available on FPGAs, they were exotic. Both for the FPGA guys and for their users. The FPGA guys had to learn how all this stuff worked, tune the (relatively) complicated analog circuits, and make it all function. Those were some of the last features to be officially released on those devices because they just took longer to get right. More than one customer was stranded waiting for parts with working high-speed I/Os.

Meanwhile, there weren’t a lot of customers who knew what to do with this stuff. The protocols were complex, and rolling your own took fortitude. And likely a stiff drink to steady the nerves. They looked to the FPGA guys for help, and the FPGA guys were looking to them for help. Gradually the FPGA guys got a handle on things and even defined their own lightweight high-speed serial protocols – Aurora for Xilinx and SerialLite for Altera. But the FPGA guys were scared to death of what customers might try to do – this collection of circuits could be put together in all kinds of scary demonic ways that may or may not have been intended. So they tried to limit the ways in which they could be used – essentially defining “sandboxes” in which customers could play. Go outside the sandbox, and you’re on your own – no support.

Consistent with this was the fact that I/Os with SERDES were available only on the highest-end devices – Stratix GX for Altera and Virtex 4 FX for Xilinx. This coupled them with the biggest densities, and, in the case of Virtex, tied them in with the built-in PowerPC processors. There were cases where customers were buying PowerPCs just to get the SERDES. [more]