Xilinx Virtex-class FPGAs feature several advanced hardwired, hard IP blocks, some of which we must protect for legal reasons. Traditionally, to allow customers to use these blocks effectively while preventing theft or tampering, we’ve offered customers black-box simulation models called SmartModels of these cores. However, some customers have found these models hard to use and note the models tend to run much slower than regular RTL models in third-party simulation environments. So with the introduction of Virtex-5 FPGAs, we now support a much faster, easier to use but protected form of simulation model called a SecureIP model.

These new models have significant ease of use and performance advantages over SmartModels but there are some differences users should become familiar with to use the SecureIP models very effectively.

Let’s look at the issues of Hard IP modeling and then review some run time and performance benchmark data on the new vs. the old models. We’ll also look at further performance speedups with FAST models and benchmark those models running on simulators from Mentor, Cadence and Synopsys. [MORE]

Introduction
Today, many applications require low-power programmable logic solutions. For this reason, many programmable logic vendors have focused on minimizing device power consumption. Of these vendors, several claim low-power superiority. However, only one can be the true leader.

In this paper, the power consumption of six competitive programmable logic devices is compared via published vendor datasheets, power-estimation tools, and real silicon measurements. In the end, this paper will prove that Actel's flash-based IGLOO® FPGAs are the undisputed low-power leaders in the industry, regardless of logic density, design configuration, or power mode.

Power Consumption Components
There are five different power components that must be considered when evaluating different FPGA vendors. Figure 1 shows these components. [MORE]

How does an IC startup overcome the learning curve of high-end EDA tools when the engineers wear several hats and can work only part-time on design?
NoblePeak Vision Corporation faced this challenge when developing its TriWave™ imager, a germanium-enhanced CMOS imager at the core of its line of night-vision products used in security, transportation and defense.

ICs for Seeing in the Dark
The founders of NoblePeak Vision discovered a way to grow defect-free germanium on a silicon substrate in such a way that it is compatible with conventional CMOS processing. They developed the technology into a low-cost imager that extends the sensitivity of silicon cameras into the short wave infrared (SWIR) band to enable low-cost day/night vision. [MORE]

Introduction
Designers are creating FPGAs that continue to increase in logic density and performance, yet their time-to-market pressures are becoming even more demanding. Computing power is not increasing as rapidly to maintain compilation times for synthesis, placement, and routing. For example, the number of logic cells in Altera ® devices has grown by 35 times and the number of memory bits by over 100 times in the last ten years, yet computing power has grown only 10 times. Larger and higher performance designs in larger FPGAs are leading to longer compilation times.

Today’s FPGA designers are expressing concerns about compilation times and achieving timing closure that previously were associated only with ASIC designs. In 2008, Altera’s largest Stratix® IV and HardCopy® IV designs are expected to reach more than twice the average gate count for ASIC designs, as shown in Figure 1. Without Altera’s efforts to reduce compilation time, these large designs would take more than a full day to compile with every design change, leading to inefficiency and wasted design time. [MORE]

Unprecedented device complexity and embedded software content are driving the need for a new hardware-assisted verification approach. EVE’s ZeBu is a breakthrough architecture that combines the strengths of traditional emulation and rapid prototyping into a unified platform for both hardware and embedded software development. For the first time a single platform and design representation can satisfy the needs of both these applications, enabling hardware designers and software developers to communicate and collaborate in a way that was never possible before. The net benefit of ZeBu’s unifying approach is to accelerate hardware/software integration well ahead of first silicon, reduce unnecessary re-spins and software revisions, and shorten time to market.

As shown in Table 1, ZeBu is much faster and more affordable than best-in-class emulation systems. ZeBu also is much easier to use, offers much higher capacity and better hardware debugging than FPGA prototyping systems. In addition, ZeBu’s integration with popular HDL simulators and with high-level of abstraction testbenches at transaction-level provides the highest performance level in the industry, reducing co-emulation overhead by at least one order of magnitude. [MORE]

Today, virtually every ASIC and ASSP is being verified using a FPGA-based prototype. That clearly takes prototyping out of its previous ad-hoc existence and puts it right next to software simulation as an essential verification tool for chip design. However, becoming a mainstream verification methodology brings with it the responsibility to adhere to standards, making the tool easily deployable and allowing integration into existing flows and environments. Moreover, in the case of prototyping, it also requires that the prototyping system is applicable and reusable for many years and for a wide variety of projects and designs.

HAPS™ (High-performance ASIC Prototyping System™) is a modular system with multi-FPGA motherboards and standard or custom-made daughter boards, which can be connected together in a variety of ways. Amongst the functions available on standard daughter boards are video processing, various memory types, A/D and D/A conversion, and interfaces to Ethernet, USB, PCI, PCI Express, and ARM. The robust and reliable hardware, together with the flexibility and I/O connectivity, and the large collection of off-the- shelf hardware modules makes it easy for ASIC designers to build their own customized ASIC prototype. [MORE]