The upshot: The Tide Organization tested password splintering and, in one study, found an increase of 14,064,094% in security as compared with “conventional, centralized alternatives.”
Passwords are this horrible thing that we can’t seem to escape. If we’re doing it right, each of the 300-odd passwords we need will be random, long, changed every month, and, of … Read More → "Passwords Rent Asunder"
What do high level synthesis, FPGAs, and the first 3D printer capable of printing fully-functional electronics have in common? This week’s podcast, of course! First up, I chat with Max Odendahl (CEO, Founder – Silexica) about ins and outs of system level understanding and optimization, what we can do with unsynthesizable C/C++ code and how we can tackle the biggest challenges in using Software (C/C++) for hardware … Read More → "Driving Optimization"
In part 1 of this series, we looked at new high-end FPGA families from Xilinx, Intel, and Achronix and discussed their underlying semiconductor processes, the type and amount of programmable logic LUT fabric, the type and amount of DSP/arithmetic resources and their applicability to AI inference acceleration tasks, the claimed TOPS/FLOPS performance capabilities, and on-chip interconnect … Read More → "High-End FPGA Showdown – Part 3"
The upshot: Trained AI models have to be adapted for specific inference implementations. New inference hardware was presented at Hot Chips by Intel, Xilinx, and Nvidia, and Mipsology has yet another inference option.
This week we bring the natural follow-on to the machine-learning (ML) training piece of Read More → "SoCs for ML Inference"