How the FPGA Came To Be, Part 6: Actel’s FPGA Story

Late in 2021, I published a five-part series titled “How the FPGA Came To Be” (referenced below). That series chronicled the development of programmable logic from the earliest days of Harris Semiconductor’s programmable diode arrays and continued through the development of bipolar PROMs, the Signetics 82S100 FPLA, MMI’s original bipolar PALs, CMOS PAL devices from Altera and Lattice Semiconductor, and finally the introduction of the … Read More → "How the FPGA Came To Be, Part 6: Actel’s FPGA Story"

Next Generation Wafers and the Future of Optical Connectivity

This week Mark Benton (TE Connectivity) joins me to chat all about rugged optical transceivers. Mark and I discuss how these transceivers can enable flexible embedded solutions, the challenges of unbalanced input and output channel counts in military and aerospace designs, and the benefits that modularity can bring to these kinds of designs. Also this week, I check out how you can take a trip to … Read More → "Next Generation Wafers and the Future of Optical Connectivity"

Open-Source AutoML for Edge AI/ML Development

I was just cogitating and ruminating on the futuristic technologies to which I was exposed when “Star Trek: The Original Series (TOS)” first graced our television screens in 1966. Things like the flip-open communicators, which predated the launch of the world’s first flip phone by 30 years.

Also, there was artificial intelligence (AI) and machine learning (ML) of a form. However, … Read More → "Open-Source AutoML for Edge AI/ML Development"

ChatGPT will not replace me – yet

An EEJournal reader recently suggested, eagerly I might add, that ChatGPT can already replace me. This statement was made even before OpenAI announced ChatGPT 4o. It’s not something that particularly worries me, knowing how these chatbots are trained. You can try to dump the entire Internet into a chatbot training session, but that does not give the chatbot wisdom, nor will it transform the chatbot into … Read More → "ChatGPT will not replace me – yet"

It’s Not Just About Protecting the Chip: How Amida is Enhancing Security throughout the Semiconductor Lifecycle

My podcast guest this week is Margaret Schmitt, General Manager of the Microelectronics Security Division at Amida. We discuss common security threats facing microelectronics devices today, the details of Amida’s flagship Achilles solution, the innovative ways that Amida is enhancing security throughout the semiconductor lifecycle, … Read More → "It’s Not Just About Protecting the Chip: How Amida is Enhancing Security throughout the Semiconductor Lifecycle"

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featured chalk talk

Trends and Solutions for Next Generation Energy Storage Systems
Sponsored by Mouser Electronics and onsemi
Increased installations of DC ultra fast chargers, the rise of distributed grid systems, and a wider adoption of residential solar installations are making robust energy storage systems more important than ever before. In this episode of Chalk Talk, Amelia Dalton, Hunter Freberg and Prasad Paruchuri from onsemi examine trends in EV chargers, solar, and energy storage systems, the role that battery storage integration plays in energy storage systems, and how onsemi is promoting innovation in the world of energy storage systems.
Jan 29, 2024
24,921 views

featured paper

Navigating design challenges: block/chip design-stage verification

Sponsored by Siemens Digital Industries Software

Explore the future of IC design with the Calibre Shift left initiative. In this paper, author David Abercrombie reveals how Siemens is changing the game for block/chip design-stage verification by moving Calibre verification and reliability analysis solutions further left in the design flow, including directly inside your P&R tool cockpit. Discover how you can reduce traditional long-loop verification iterations, saving time, improving accuracy, and dramatically boosting productivity.

Click here to read more

featured video

How NV5, NVIDIA, and Cadence Collaboration Optimizes Data Center Efficiency, Performance, and Reliability

Sponsored by Cadence Design Systems

Deploying data centers with AI high-density workloads and ensuring they are capable for anticipated power trends requires insight. Creating a digital twin using the Cadence Reality Digital Twin Platform helped plan the deployment of current workloads and future-proof the investment. Learn about the collaboration between NV5, NVIDIA, and Cadence to optimize data center efficiency, performance, and reliability. 

Click here for more information about Cadence Data Center Solutions

discussion
Posted on Jul 24 at 6:42am by Steven Leibson
Hiya Duke, Duke, Duke, DukeofEarl. My good friend Robert Bielby, who was also my first manager at Xilinx, explained to me how tone deaf the early FPGA software developers were about pinning the I/O pin definitions between iterations of an FPGA configuration. I'm glad you found a workaround. I ...
Posted on Jul 23 at 9:33am by DukeofEarl
Great series Steven, on both this and the history of EDA. We have something in common, both having worked for Cadnetix and both being Steven's though I worked as an Applications Engineer in the UK... One of the problems biggest problems we had with early larger FPGAs, especially a large ...
Posted on Jul 19 at 2:54pm by Max Maxfield
Thank goodness -- at first I thought you were saying I'd made a mistake in my column LOL
Posted on Jul 19 at 2:54pm by Max Maxfield
Hi RedBarnDesigner -- thanks so much for your kind words. The stuff from Cartesiam was really good, so much so that they were snapped up by STMicro in 2021. Since that time, a bunch of other companies have started to do some very interesting things in this area. I'm not going ...
Posted on Jul 18 at 1:50pm by Karl Stevens
I could really get into designing using the FPGA memory blocks. Pipelining has reached the clock speed limit and HLS may never be truly usable. Using HDL for design entry was and still is a colossal blunder. There is no real debugging capability in the tool chain other than waveforms. ...
Posted on Jul 18 at 9:54am by RedBarnDesigner
2-pet??? That's a cat and a dog isn't it! (oops - watch out for the exclamation mark police!) What my brain meant to say was 2-part but my typing fingers got into a dispute with my brain and guess who won!
Posted on Jul 18 at 9:51am by RedBarnDesigner
Hi Max, I have just re-read this 2-pet mini-series after reading your latest post. This article has really stuck with me. I find this really impressive. With a big fast CPU and some signal processing, I can easily believe that you can pick up any anomalies and send an alert. ...
Posted on Jul 16 at 1:15pm by narwal
Insightful article, Steven! Thank you. In the brouhaha of AI drumming, people are forgetting that the current prowess of AI is surface level. But people often underestimate what can it do in 10 years timeframe. I'm working on a power product which is attempting to answer this question for a very ...
Posted on Jul 16 at 6:21am by Steven Leibson
You have more faith in management than I do, fpgareader.
Posted on Jul 15 at 11:28pm by fpgareader
I refer you to Dilbert. The key phrase is ‘expert’. AI output almost certainly appears to be expert knowledge to any manager senior enough to have decision-making responsibility for AI deployment. So we rely on that exec being expert enough in ‘management’ to know that they should not rely on ...
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featured blogs
Jul 20, 2024
If you are looking for great technology-related reads, here are some offerings that I cannot recommend highly enough....
Versatile S32G3 Processors for Automotive and Beyond
In this episode of Chalk Talk, Amelia Dalton and Brian Carlson from NXP investigate NXP’s S32G3 vehicle network processors that combine ASIL D safety, hardware security, high-performance real-time and application processing and network acceleration. They explore how these processors support many vehicle needs simultaneously, the specific benefits they bring to autonomous drive and ADAS applications, and how you can get started developing with these processors today.
Jul 24, 2024
38 views
Accelerating Tapeouts with Synopsys Cloud and AI
Sponsored by Synopsys
In this episode of Chalk Talk, Amelia Dalton and Vikram Bhatia from Synopsys explore how you can accelerate your next tapeout with Synopsys Cloud and AI. They also discuss new enhancements and customer use cases that leverage AI with hybrid cloud deployment scenarios, and how this platform can help CAD managers and engineers reduce licensing overheads and seamlessly run complex EDA design flows through Synopsys Cloud.
Jul 8, 2024
2,873 views
Developing a Secured Matter Device with the OPTIGA™ Trust M MTR Shield
Sponsored by Mouser Electronics and Infineon
In this episode of Chalk Talk, Amelia Dalton and Johannes Koblbauer from Infineon explore how you can add Matter and security to your next smart home project with the OPTIGA™ Trust M MTR shield. They also investigate the steps involved in the OPTIGA™ Trust M Matter design process, the details of the OPTIGA™ Trust M Matter evaluation board and how you can get started on your next Matter IoT device.
Jul 2, 2024
3,496 views
Shift Left Block/Chip Design with Calibre
In this episode of Chalk Talk, Amelia Dalton and David Abercrombie from Siemens EDA explore the multitude of benefits that shifting left with Calibre can bring to chip and block design. They investigate how Calibre can impact DRC verification, early design error debug, and optimize the configuration and management of multiple jobs for run time improvement.
Jun 18, 2024
5,283 views
ROHM’s 3rd Gen 650V IGBT for a Wide range of Applications: RGW and RGWS Series
In this episode of Chalk Talk, Amelia Dalton and Heath Ogurisu from ROHM Semiconductor investigate the benefits of ROHM Semiconductor’s RGW and RGWS Series of IGBTs. They explore how the soft switching of these hybrid IGBTs contribute to energy savings and power generation efficiency and why these IGBTs provide a well-balanced solution for switching and cost.
Jun 5, 2024
7,010 views
Easily Connect to AWS Cloud with ExpressLink Over Wi-Fi
Sponsored by Mouser Electronics and AWS and u-blox
In this episode of Chalk Talk, Amelia Dalton, Lucio Di Jasio from AWS and Magnus Johansson from u-blox explore common pitfalls of designing an IoT device from scratch, the benefits that AWS IoT ExpressLink brings to IoT device design, and how the the NORA-W2 AWS IoT ExpressLink multiradio modules can make retrofitting an already existing design into a smart AWS connected device easier than ever before.
May 30, 2024
7,571 views